STM32WB55 Peripheral Coverage

Overall: 660/4947 fields covered

ADC

0x50040000: Analog to Digital Converter instance 1

7/135 fields covered. Toggle Registers.

ISR

ADC interrupt and status register

Offset: 0x0, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					JQOVF rw	AWD3 rw	AWD2 rw	AWD1 rw	JEOS rw	JEOC rw	OVR rw	EOS rw	EOC rw	EOSMP rw	ADRDY rw

Toggle Fields.

ADRDY

Bit 0: ADC ready flag.

EOSMP

Bit 1: ADC group regular end of sampling flag.

EOC

Bit 2: ADC group regular end of unitary conversion flag.

EOS

Bit 3: ADC group regular end of sequence conversions flag.

OVR

Bit 4: ADC group regular overrun flag.

JEOC

Bit 5: ADC group injected end of unitary conversion flag.

JEOS

Bit 6: ADC group injected end of sequence conversions flag.

AWD1

Bit 7: ADC analog watchdog 1 flag.

AWD2

Bit 8: ADC analog watchdog 2 flag.

AWD3

Bit 9: ADC analog watchdog 3 flag.

JQOVF

Bit 10: ADC group injected contexts queue overflow flag.

IER

ADC interrupt enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					JQOVFIE rw	AWD3IE rw	AWD2IE rw	AWD1IE rw	JEOSIE rw	JEOCIE rw	OVRIE rw	EOSIE rw	EOCIE rw	EOSMPIE rw	ADRDYIE rw

Toggle Fields.

ADRDYIE

Bit 0: ADC ready interrupt.

EOSMPIE

Bit 1: ADC group regular end of sampling interrupt.

EOCIE

Bit 2: ADC group regular end of unitary conversion interrupt.

EOSIE

Bit 3: ADC group regular end of sequence conversions interrupt.

OVRIE

Bit 4: ADC group regular overrun interrupt.

JEOCIE

Bit 5: ADC group injected end of unitary conversion interrupt.

JEOSIE

Bit 6: ADC group injected end of sequence conversions interrupt.

AWD1IE

Bit 7: ADC analog watchdog 1 interrupt.

AWD2IE

Bit 8: ADC analog watchdog 2 interrupt.

AWD3IE

Bit 9: ADC analog watchdog 3 interrupt.

JQOVFIE

Bit 10: ADC group injected contexts queue overflow interrupt.

CR

ADC control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADCAL rw	ADCALDIF rw	DEEPPWD rw	ADVREGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										JADSTP rw	ADSTP rw	JADSTART rw	ADSTART rw	ADDIS rw	ADEN rw

Toggle Fields.

ADEN

Bit 0: ADC enable.

ADDIS

Bit 1: ADC disable.

ADSTART

Bit 2: ADC group regular conversion start.

JADSTART

Bit 3: ADC group injected conversion start.

ADSTP

Bit 4: ADC group regular conversion stop.

JADSTP

Bit 5: ADC group injected conversion stop.

ADVREGEN

Bit 28: ADC voltage regulator enable.

DEEPPWD

Bit 29: ADC deep power down enable.

ADCALDIF

Bit 30: ADC differential mode for calibration.

ADCAL

Bit 31: ADC calibration.

CFGR

ADC configuration register 1

Offset: 0xC, reset: 0x80000000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
JQDIS rw	AWDCH1CH rw					JAUTO rw	JAWD1EN rw	AWD1EN rw	AWD1SGL rw	JQM rw	JDISCEN rw	DISCNUM rw			DISCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	AUTDLY rw	CONT rw	OVRMOD rw	EXTEN rw		EXTSEL rw				ALIGN rw	RES rw			DMACFG rw	DMAEN rw

Toggle Fields.

DMAEN

Bit 0: ADC DMA transfer enable.

DMACFG

Bit 1: ADC DMA transfer configuration.

RES

Bits 3-4: ADC data resolution.

ALIGN

Bit 5: ADC data alignement.

EXTSEL

Bits 6-9: ADC group regular external trigger source.

EXTEN

Bits 10-11: ADC group regular external trigger polarity.

OVRMOD

Bit 12: ADC group regular overrun configuration.

CONT

Bit 13: ADC group regular continuous conversion mode.

AUTDLY

Bit 14: ADC low power auto wait.

DISCEN

Bit 16: ADC group regular sequencer discontinuous mode.

DISCNUM

Bits 17-19: ADC group regular sequencer discontinuous number of ranks.

JDISCEN

Bit 20: ADC group injected sequencer discontinuous mode.

JQM

Bit 21: ADC group injected contexts queue mode.

AWD1SGL

Bit 22: ADC analog watchdog 1 monitoring a single channel or all channels.

AWD1EN

Bit 23: ADC analog watchdog 1 enable on scope ADC group regular.

JAWD1EN

Bit 24: ADC analog watchdog 1 enable on scope ADC group injected.

JAUTO

Bit 25: ADC group injected automatic trigger mode.

AWDCH1CH

Bits 26-30: ADC analog watchdog 1 monitored channel selection.

JQDIS

Bit 31: ADC group injected contexts queue disable.

CFGR2

ADC configuration register 2

Offset: 0x10, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					ROVSM rw	TOVS rw	OVSS rw				OVSR rw			JOVSE rw	ROVSE rw

Toggle Fields.

ROVSE

Bit 0: ADC oversampler enable on scope ADC group regular.

JOVSE

Bit 1: ADC oversampler enable on scope ADC group injected.

OVSR

Bits 2-4: ADC oversampling ratio.

OVSS

Bits 5-8: ADC oversampling shift.

TOVS

Bit 9: ADC oversampling discontinuous mode (triggered mode) for ADC group regular.

ROVSM

Bit 10: ADC oversampling mode managing interlaced conversions of ADC group regular and group injected.

SMPR1

ADC sampling time register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		SMP9 rw			SMP8 rw			SMP7 rw			SMP6 rw			SMP5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP5 rw	SMP4 rw			SMP3 rw			SMP2 rw			SMP1 rw

Toggle Fields.

SMP1

Bits 3-5: ADC channel 1 sampling time selection.

SMP2

Bits 6-8: ADC channel 2 sampling time selection.

SMP3

Bits 9-11: ADC channel 3 sampling time selection.

SMP4

Bits 12-14: ADC channel 4 sampling time selection.

SMP5

Bits 15-17: ADC channel 5 sampling time selection.

SMP6

Bits 18-20: ADC channel 6 sampling time selection.

SMP7

Bits 21-23: ADC channel 7 sampling time selection.

SMP8

Bits 24-26: ADC channel 8 sampling time selection.

SMP9

Bits 27-29: ADC channel 9 sampling time selection.

SMPR2

ADC sampling time register 2

Offset: 0x18, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					SMP18 rw			SMP17 rw			SMP16 rw			SMP15 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SMP15 rw	SMP14 rw			SMP13 rw			SMP12 rw			SMP11 rw			SMP10 rw

Toggle Fields.

SMP10

Bits 0-2: ADC channel 10 sampling time selection.

SMP11

Bits 3-5: ADC channel 11 sampling time selection.

SMP12

Bits 6-8: ADC channel 12 sampling time selection.

SMP13

Bits 9-11: ADC channel 13 sampling time selection.

SMP14

Bits 12-14: ADC channel 14 sampling time selection.

SMP15

Bits 15-17: ADC channel 15 sampling time selection.

SMP16

Bits 18-20: ADC channel 16 sampling time selection.

SMP17

Bits 21-23: ADC channel 17 sampling time selection.

SMP18

Bits 24-26: ADC channel 18 sampling time selection.

TR1

ADC analog watchdog 1 threshold register

Offset: 0x20, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				HT1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LT1 rw

Toggle Fields.

LT1

Bits 0-11: ADC analog watchdog 1 threshold low.

HT1

Bits 16-27: ADC analog watchdog 1 threshold high.

TR2

ADC analog watchdog 2 threshold register

Offset: 0x24, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								HT2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LT2 rw

Toggle Fields.

LT2

Bits 0-7: ADC analog watchdog 2 threshold low.

HT2

Bits 16-23: ADC analog watchdog 2 threshold high.

TR3

ADC analog watchdog 3 threshold register

Offset: 0x28, reset: 0x0FFF0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								HT3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								LT3 rw

Toggle Fields.

LT3

Bits 0-7: ADC analog watchdog 3 threshold low.

HT3

Bits 16-23: ADC analog watchdog 3 threshold high.

SQR1

ADC group regular sequencer ranks register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ4 rw						SQ3 rw						SQ2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ2 rw					SQ1 rw							L3 rw

Toggle Fields.

L3

Bits 0-3: L3.

SQ1

Bits 6-10: ADC group regular sequencer rank 1.

SQ2

Bits 12-16: ADC group regular sequencer rank 2.

SQ3

Bits 18-22: ADC group regular sequencer rank 3.

SQ4

Bits 24-28: ADC group regular sequencer rank 4.

SQR2

ADC group regular sequencer ranks register 2

Offset: 0x34, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ9 rw						SQ8 rw						SQ7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ7 rw					SQ6 rw						SQ5 rw

Toggle Fields.

SQ5

Bits 0-4: ADC group regular sequencer rank 5.

SQ6

Bits 6-10: ADC group regular sequencer rank 6.

SQ7

Bits 12-16: ADC group regular sequencer rank 7.

SQ8

Bits 18-22: ADC group regular sequencer rank 8.

SQ9

Bits 24-28: ADC group regular sequencer rank 9.

SQR3

ADC group regular sequencer ranks register 3

Offset: 0x38, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SQ14 rw						SQ13 rw						SQ12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SQ12 rw					SQ11 rw						SQ10 rw

Toggle Fields.

SQ10

Bits 0-4: ADC group regular sequencer rank 10.

SQ11

Bits 6-10: ADC group regular sequencer rank 11.

SQ12

Bits 12-16: ADC group regular sequencer rank 12.

SQ13

Bits 18-22: ADC group regular sequencer rank 13.

SQ14

Bits 24-28: ADC group regular sequencer rank 14.

SQR4

ADC group regular sequencer ranks register 4

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					SQ16 rw						SQ15 rw

Toggle Fields.

SQ15

Bits 0-4: ADC group regular sequencer rank 15.

SQ16

Bits 6-10: ADC group regular sequencer rank 16.

DR

ADC group regular conversion data register

Offset: 0x40, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RDATA_7_15 r										RDATA_0_6 rw

Toggle Fields.

RDATA_0_6

Bits 0-5: Regular Data converted 0_6.

RDATA_7_15

Bits 7-15: 15.

JSQR

ADC group injected sequencer register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	JSQ4 rw						JSQ3 rw						JSQ2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JSQ2 rw			JSQ1 rw					JEXTEN rw		JEXTSEL rw				JL rw

Toggle Fields.

JL

Bits 0-1: ADC group injected sequencer scan length.

JEXTSEL

Bits 2-5: ADC group injected external trigger source.

JEXTEN

Bits 6-7: ADC group injected external trigger polarity.

JSQ1

Bits 8-12: ADC group injected sequencer rank 1.

JSQ2

Bits 14-18: ADC group injected sequencer rank 2.

JSQ3

Bits 20-24: ADC group injected sequencer rank 3.

JSQ4

Bits 26-30: ADC group injected sequencer rank 4.

OFR1

ADC offset number 1 register

Offset: 0x60, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET1_EN rw	OFFSET1_CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OFFSET1 rw

Toggle Fields.

OFFSET1

Bits 0-11: ADC offset number 1 offset level.

OFFSET1_CH

Bits 26-30: ADC offset number 1 channel selection.

OFFSET1_EN

Bit 31: ADC offset number 1 enable.

OFR2

ADC offset number 2 register

Offset: 0x64, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET2_EN rw	OFFSET2_CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OFFSET2 rw

Toggle Fields.

OFFSET2

Bits 0-11: ADC offset number 2 offset level.

OFFSET2_CH

Bits 26-30: ADC offset number 2 channel selection.

OFFSET2_EN

Bit 31: ADC offset number 2 enable.

OFR3

ADC offset number 3 register

Offset: 0x68, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET3_EN rw	OFFSET3_CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OFFSET3 rw

Toggle Fields.

OFFSET3

Bits 0-11: ADC offset number 3 offset level.

OFFSET3_CH

Bits 26-30: ADC offset number 3 channel selection.

OFFSET3_EN

Bit 31: ADC offset number 3 enable.

OFR4

ADC offset number 4 register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OFFSET4_EN rw	OFFSET4_CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				OFFSET4 rw

Toggle Fields.

OFFSET4

Bits 0-11: ADC offset number 4 offset level.

OFFSET4_CH

Bits 26-30: ADC offset number 4 channel selection.

OFFSET4_EN

Bit 31: ADC offset number 4 enable.

JDR1

ADC group injected sequencer rank 1 register

Offset: 0x80, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA1 r

Toggle Fields.

JDATA1

Bits 0-15: ADC group injected sequencer rank 1 conversion data.

JDR2

ADC group injected sequencer rank 2 register

Offset: 0x84, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA2 r

Toggle Fields.

JDATA2

Bits 0-15: ADC group injected sequencer rank 2 conversion data.

JDR3

ADC group injected sequencer rank 3 register

Offset: 0x88, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA3 r

Toggle Fields.

JDATA3

Bits 0-15: ADC group injected sequencer rank 3 conversion data.

JDR4

ADC group injected sequencer rank 4 register

Offset: 0x8C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
JDATA4 r

Toggle Fields.

JDATA4

Bits 0-15: ADC group injected sequencer rank 4 conversion data.

AWD2CR

ADC analog watchdog 2 configuration register

Offset: 0xA0, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													AWD2CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD2CH rw

Toggle Fields.

AWD2CH

Bits 0-18: ADC analog watchdog 2 monitored channel selection.

AWD3CR

ADC analog watchdog 3 configuration register

Offset: 0xA4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													AWD3CH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AWD3CH rw

Toggle Fields.

AWD3CH

Bits 0-18: ADC analog watchdog 3 monitored channel selection.

DIFSEL

ADC channel differential or single-ended mode selection register

Offset: 0xB0, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DIFSEL_16_18 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DIFSEL_1_15 rw															DIFSEL_0 r

Toggle Fields.

DIFSEL_0

Bit 0: ADC channel differential or single-ended mode for channel 0.

DIFSEL_1_15

Bits 1-15: ADC channel differential or single-ended mode for channels 1 to 15.

DIFSEL_16_18

Bits 16-18: ADC channel differential or single-ended mode for channels 18 to 16.

CALFACT

ADC calibration factors register

Offset: 0xB4, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									CALFACT_D rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									CALFACT_S rw

Toggle Fields.

CALFACT_S

Bits 0-6: ADC calibration factor in single-ended mode.

CALFACT_D

Bits 16-22: ADC calibration factor in differential mode.

CCR

ADC common control register

Offset: 0x308, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							VBATEN rw	TSEN rw	VREFEN rw	PRESC rw				CKMODE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

CKMODE

Bits 16-17: ADC clock mode.

PRESC

Bits 18-21: ADC prescaler.

VREFEN

Bit 22: VREFEN.

TSEN

Bit 23: Temperature sensor enable.

VBATEN

Bit 24: VBAT enable.

AES1

0x50060000: Advanced encryption standard hardware accelerator 1

13/48 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								NPBLB rw					KEYSIZE rw		CHMOD2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	GCMPH rw		DMAOUTEN rw	DMAINEN rw	ERRIE rw	CCFIE rw	ERRC rw	CCFC rw	CHMOD10 rw		MODE rw		DATATYPE rw		EN rw

Toggle Fields.

EN

Bit 0: AES enable.

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

MODE

Bits 3-4: AES operating mode.

CHMOD10

Bits 5-6: AES chaining mode Bit1 Bit0.

CCFC

Bit 7: Computation Complete Flag Clear.

ERRC

Bit 8: Error clear.

CCFIE

Bit 9: CCF flag interrupt enable.

ERRIE

Bit 10: Error interrupt enable.

DMAINEN

Bit 11: Enable DMA management of data input phase.

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

GCMPH

Bits 13-14: Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected.

CHMOD2

Bit 16: AES chaining mode Bit2.

KEYSIZE

Bit 18: Key size selection.

NPBLB

Bits 20-23: Number of padding bytes in last block of payload.

SR

status register

Offset: 0x4, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BUSY r	WRERR r	RDERR r	CCF r

Toggle Fields.

CCF

Bit 0: Computation complete flag.

RDERR

Bit 1: Read error flag.

WRERR

Bit 2: Write error flag.

BUSY

Bit 3: Busy flag.

DINR

data input register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_DINR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_DINR rw

Toggle Fields.

AES_DINR

Bits 0-31: Data Input Register.

DOUTR

data output register

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_DOUTR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_DOUTR r

Toggle Fields.

AES_DOUTR

Bits 0-31: Data output register.

KEYR0

key register 0

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR0 rw

Toggle Fields.

AES_KEYR0

Bits 0-31: Data Output Register (LSB key [31:0]).

KEYR1

key register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR1 rw

Toggle Fields.

AES_KEYR1

Bits 0-31: AES key register (key [63:32]).

KEYR2

key register 2

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR2 rw

Toggle Fields.

AES_KEYR2

Bits 0-31: AES key register (key [95:64]).

KEYR3

key register 3

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR3 rw

Toggle Fields.

AES_KEYR3

Bits 0-31: AES key register (MSB key [127:96]).

IVR0

initialization vector register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR0 rw

Toggle Fields.

AES_IVR0

Bits 0-31: initialization vector register (LSB IVR [31:0]).

IVR1

initialization vector register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR1 rw

Toggle Fields.

AES_IVR1

Bits 0-31: Initialization Vector Register (IVR [63:32]).

IVR2

initialization vector register 2

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR2 rw

Toggle Fields.

AES_IVR2

Bits 0-31: Initialization Vector Register (IVR [95:64]).

IVR3

initialization vector register 3

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR3 rw

Toggle Fields.

AES_IVR3

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

KEYR4

key register 4

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR4 rw

Toggle Fields.

AES_KEYR4

Bits 0-31: AES key register (MSB key [159:128]).

KEYR5

key register 5

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR5 rw

Toggle Fields.

AES_KEYR5

Bits 0-31: AES key register (MSB key [191:160]).

KEYR6

key register 6

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR6 rw

Toggle Fields.

AES_KEYR6

Bits 0-31: AES key register (MSB key [223:192]).

KEYR7

key register 7

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR7 rw

Toggle Fields.

AES_KEYR7

Bits 0-31: AES key register (MSB key [255:224]).

SUSP0R

AES suspend register 0

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP0R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP0R rw

Toggle Fields.

AES_SUSP0R

Bits 0-31: AES suspend register 0.

SUSP1R

AES suspend register 1

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP1R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP1R rw

Toggle Fields.

AES_SUSP1R

Bits 0-31: AES suspend register 1.

SUSP2R

AES suspend register 2

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP2R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP2R rw

Toggle Fields.

AES_SUSP2R

Bits 0-31: AES suspend register 2.

SUSP3R

AES suspend register 3

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP3R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP3R rw

Toggle Fields.

AES_SUSP3R

Bits 0-31: AES suspend register 3.

SUSP4R

AES suspend register 4

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP4R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP4R rw

Toggle Fields.

AES_SUSP4R

Bits 0-31: AES suspend register 4.

SUSP5R

AES suspend register 5

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP5R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP5R rw

Toggle Fields.

AES_SUSP5R

Bits 0-31: AES suspend register 5.

SUSP6R

AES suspend register 6

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP6R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP6R rw

Toggle Fields.

AES_SUSP6R

Bits 0-31: AES suspend register 6.

SUSP7R

AES suspend register 7

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP7R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP7R rw

Toggle Fields.

AES_SUSP7R

Bits 0-31: AES suspend register 7.

HWCFR

AES hardware configuration register

Offset: 0x3F0, reset: 0x00000002, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CFG4 r				CFG3 r				CFG2 r				CFG1 r

Toggle Fields.

CFG1

Bits 0-3: HW Generic 1.

CFG2

Bits 4-7: HW Generic 2.

CFG3

Bits 8-11: HW Generic 3.

CFG4

Bits 12-15: HW Generic 4.

VERR

AES version register

Offset: 0x3F4, reset: 0x00000010, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields.

MINREV

Bits 0-3: Minor revision.

MAJREV

Bits 4-7: Major revision.

IPIDR

AES identification register

Offset: 0x3F8, reset: 0x00170023, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle Fields.

ID

Bits 0-31: Identification code.

SIDR

AES size ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle Fields.

ID

Bits 0-31: Size Identification code.

AES2

0x58001800: Advanced encryption standard hardware accelerator 1

13/48 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								NPBLB rw					KEYSIZE rw		CHMOD2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	GCMPH rw		DMAOUTEN rw	DMAINEN rw	ERRIE rw	CCFIE rw	ERRC rw	CCFC rw	CHMOD10 rw		MODE rw		DATATYPE rw		EN rw

Toggle Fields.

EN

Bit 0: AES enable.

DATATYPE

Bits 1-2: Data type selection (for data in and data out to/from the cryptographic block).

MODE

Bits 3-4: AES operating mode.

CHMOD10

Bits 5-6: AES chaining mode Bit1 Bit0.

CCFC

Bit 7: Computation Complete Flag Clear.

ERRC

Bit 8: Error clear.

CCFIE

Bit 9: CCF flag interrupt enable.

ERRIE

Bit 10: Error interrupt enable.

DMAINEN

Bit 11: Enable DMA management of data input phase.

DMAOUTEN

Bit 12: Enable DMA management of data output phase.

GCMPH

Bits 13-14: Used only for GCM, CCM and GMAC algorithms and has no effect when other algorithms are selected.

CHMOD2

Bit 16: AES chaining mode Bit2.

KEYSIZE

Bit 18: Key size selection.

NPBLB

Bits 20-23: Number of padding bytes in last block of payload.

SR

status register

Offset: 0x4, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BUSY r	WRERR r	RDERR r	CCF r

Toggle Fields.

CCF

Bit 0: Computation complete flag.

RDERR

Bit 1: Read error flag.

WRERR

Bit 2: Write error flag.

BUSY

Bit 3: Busy flag.

DINR

data input register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_DINR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_DINR rw

Toggle Fields.

AES_DINR

Bits 0-31: Data Input Register.

DOUTR

data output register

Offset: 0xC, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_DOUTR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_DOUTR r

Toggle Fields.

AES_DOUTR

Bits 0-31: Data output register.

KEYR0

key register 0

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR0 rw

Toggle Fields.

AES_KEYR0

Bits 0-31: Data Output Register (LSB key [31:0]).

KEYR1

key register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR1 rw

Toggle Fields.

AES_KEYR1

Bits 0-31: AES key register (key [63:32]).

KEYR2

key register 2

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR2 rw

Toggle Fields.

AES_KEYR2

Bits 0-31: AES key register (key [95:64]).

KEYR3

key register 3

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR3 rw

Toggle Fields.

AES_KEYR3

Bits 0-31: AES key register (MSB key [127:96]).

IVR0

initialization vector register 0

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR0 rw

Toggle Fields.

AES_IVR0

Bits 0-31: initialization vector register (LSB IVR [31:0]).

IVR1

initialization vector register 1

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR1 rw

Toggle Fields.

AES_IVR1

Bits 0-31: Initialization Vector Register (IVR [63:32]).

IVR2

initialization vector register 2

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR2 rw

Toggle Fields.

AES_IVR2

Bits 0-31: Initialization Vector Register (IVR [95:64]).

IVR3

initialization vector register 3

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_IVR3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_IVR3 rw

Toggle Fields.

AES_IVR3

Bits 0-31: Initialization Vector Register (MSB IVR [127:96]).

KEYR4

key register 4

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR4 rw

Toggle Fields.

AES_KEYR4

Bits 0-31: AES key register (MSB key [159:128]).

KEYR5

key register 5

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR5 rw

Toggle Fields.

AES_KEYR5

Bits 0-31: AES key register (MSB key [191:160]).

KEYR6

key register 6

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR6 rw

Toggle Fields.

AES_KEYR6

Bits 0-31: AES key register (MSB key [223:192]).

KEYR7

key register 7

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_KEYR7 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_KEYR7 rw

Toggle Fields.

AES_KEYR7

Bits 0-31: AES key register (MSB key [255:224]).

SUSP0R

AES suspend register 0

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP0R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP0R rw

Toggle Fields.

AES_SUSP0R

Bits 0-31: AES suspend register 0.

SUSP1R

AES suspend register 1

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP1R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP1R rw

Toggle Fields.

AES_SUSP1R

Bits 0-31: AES suspend register 1.

SUSP2R

AES suspend register 2

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP2R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP2R rw

Toggle Fields.

AES_SUSP2R

Bits 0-31: AES suspend register 2.

SUSP3R

AES suspend register 3

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP3R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP3R rw

Toggle Fields.

AES_SUSP3R

Bits 0-31: AES suspend register 3.

SUSP4R

AES suspend register 4

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP4R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP4R rw

Toggle Fields.

AES_SUSP4R

Bits 0-31: AES suspend register 4.

SUSP5R

AES suspend register 5

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP5R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP5R rw

Toggle Fields.

AES_SUSP5R

Bits 0-31: AES suspend register 5.

SUSP6R

AES suspend register 6

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP6R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP6R rw

Toggle Fields.

AES_SUSP6R

Bits 0-31: AES suspend register 6.

SUSP7R

AES suspend register 7

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AES_SUSP7R rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AES_SUSP7R rw

Toggle Fields.

AES_SUSP7R

Bits 0-31: AES suspend register 7.

HWCFR

AES hardware configuration register

Offset: 0x60, reset: 0x00000002, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CFG4 r				CFG3 r				CFG2 r				CFG1 r

Toggle Fields.

CFG1

Bits 0-3: HW Generic 1.

CFG2

Bits 4-7: HW Generic 2.

CFG3

Bits 8-11: HW Generic 3.

CFG4

Bits 12-15: HW Generic 4.

VERR

AES version register

Offset: 0x64, reset: 0x00000010, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields.

MINREV

Bits 0-3: Minor revision.

MAJREV

Bits 4-7: Major revision.

IPIDR

AES identification register

Offset: 0x68, reset: 0x00170023, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle Fields.

ID

Bits 0-31: Identification code.

SIDR

AES size ID register

Offset: 0x6C, reset: 0x00170023, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle Fields.

ID

Bits 0-31: Size Identification code.

COMP

0x40010200: Comparator instance 1

2/25 fields covered. Toggle Registers.

COMP1_CSR

Comparator control and status register

Offset: 0x0, reset: 0x00000000, access: Unspecified

1/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP1_LOCK rw	COMP1_VALUE r				COMP1_INMESEL rw			COMP1_SCALEN rw	COMP1_BRGEN rw		COMP1_BLANKING rw			COMP1_HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP1_POLARITY rw							COMP1_INPSEL rw		COMP1_INMSEL rw			COMP1_PWRMODE rw			COMP1_EN rw

Toggle Fields.

COMP1_EN

Bit 0: Comparator enable.

COMP1_PWRMODE

Bits 2-3: Comparator power mode.

COMP1_INMSEL

Bits 4-6: Comparator input minus selection.

COMP1_INPSEL

Bits 7-8: Comparator input plus selection.

COMP1_POLARITY

Bit 15: Comparator output polarity.

COMP1_HYST

Bits 16-17: Comparator hysteresis.

COMP1_BLANKING

Bits 18-20: Comparator blanking source.

COMP1_BRGEN

Bit 22: Comparator voltage scaler enable.

COMP1_SCALEN

Bit 23: Comparator scaler bridge enable.

COMP1_INMESEL

Bits 25-26: Comparator input minus extended selection.

COMP1_VALUE

Bit 30: Comparator output level.

COMP1_LOCK

Bit 31: Comparator lock.

COMP2_CSR

Comparator 2 control and status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

1/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
COMP2_LOCK rw	COMP2_VALUE r				COMP2_INMESEL rw			COMP2_SCALEN rw	COMP2_BRGEN rw		COMP2_BLANKING rw			COMP2_HYST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP2_POLARITY rw						COMP2_WINMODE rw	COMP2_INPSEL rw			COMP2_INMSEL rw		COMP2_PWRMODE rw			COMP2_EN rw

Toggle Fields.

COMP2_EN

Bit 0: Comparator 2 enable bit.

COMP2_PWRMODE

Bits 2-3: Power Mode of the comparator 2.

COMP2_INMSEL

Bits 4-5: Comparator 2 input minus selection bits.

COMP2_INPSEL

Bits 7-8: Comparator 1 input plus selection bit.

COMP2_WINMODE

Bit 9: Windows mode selection bit.

COMP2_POLARITY

Bit 15: Comparator 2 polarity selection bit.

COMP2_HYST

Bits 16-17: Comparator 2 hysteresis selection bits.

COMP2_BLANKING

Bits 18-20: Comparator 2 blanking source selection bits.

COMP2_BRGEN

Bit 22: Scaler bridge enable.

COMP2_SCALEN

Bit 23: Voltage scaler enable bit.

COMP2_INMESEL

Bits 25-26: comparator 2 input minus extended selection bits..

COMP2_VALUE

Bit 30: Comparator 2 output status bit.

COMP2_LOCK

Bit 31: CSR register lock bit.

CRC

0x40023000: Cyclic redundancy check calculation unit

0/8 fields covered. Toggle Registers.

DR

Data register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle Fields.

DR

Bits 0-31: Data register bits.

IDR

Independent data register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR rw

Toggle Fields.

IDR

Bits 0-31: General-purpose 32-bit data register bits.

CR

Control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REV_OUT rw	REV_IN rw		POLYSIZE rw				RESET rw

Toggle Fields.

RESET

Bit 0: RESET bit.

POLYSIZE

Bits 3-4: Polynomial size.

REV_IN

Bits 5-6: Reverse input data.

REV_OUT

Bit 7: Reverse output data.

INIT

Initial CRC value

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CRC_INIT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRC_INIT rw

Toggle Fields.

CRC_INIT

Bits 0-31: Programmable initial CRC value.

POL

polynomial

Offset: 0x14, reset: 0x04C11DB7, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
POL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
POL rw

Toggle Fields.

POL

Bits 0-31: Programmable polynomial.

CRS

0x40006000: Clock recovery system

9/26 fields covered. Toggle Registers.

CR

CRS control register

Offset: 0x0, reset: 0x00002000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		TRIM rw						SWSYNC rw	AUTOTRIMEN rw	CEN rw		ESYNCIE rw	ERRIE rw	SYNCWARNIE rw	SYNCOKIE rw

Toggle Fields.

SYNCOKIE

Bit 0: SYNC event OK interrupt enable.

SYNCWARNIE

Bit 1: SYNC warning interrupt enable.

ERRIE

Bit 2: Synchronization or trimming error interrupt enable.

ESYNCIE

Bit 3: Expected SYNC interrupt enable.

CEN

Bit 5: Frequency error counter enable.

AUTOTRIMEN

Bit 6: Automatic trimming enable.

SWSYNC

Bit 7: Automatic trimming enable.

TRIM

Bits 8-13: HSI48 oscillator smooth trimming.

CFGR

CRS configuration register

Offset: 0x4, reset: 0x2022BB7F, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SYNCPOL rw		SYNCSRC rw			SYNCDIV rw			FELIM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle Fields.

RELOAD

Bits 0-15: Counter reload value.

FELIM

Bits 16-23: Frequency error limit.

SYNCDIV

Bits 24-26: SYNCDIV.

SYNCSRC

Bits 28-29: SYNC signal source selection.

SYNCPOL

Bit 31: SYNC polarity selection.

ISR

CRS interrupt and status register

Offset: 0x8, reset: 0x00000000, access: read-only

9/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FECAP r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FEDIR r					TRIMOVF r	SYNCMISS r	SYNCERR r					ESYNCF r	ERRF r	SYNCWARNF r	SYNCOKF r

Toggle Fields.

SYNCOKF

Bit 0: SYNC event OK flag.

SYNCWARNF

Bit 1: SYNC warning flag.

ERRF

Bit 2: Error flag.

ESYNCF

Bit 3: Expected SYNC flag.

SYNCERR

Bit 8: SYNC error.

SYNCMISS

Bit 9: SYNC missed.

TRIMOVF

Bit 10: Trimming overflow or underflow.

FEDIR

Bit 15: Frequency error direction.

FECAP

Bits 16-31: Frequency error capture.

ICR

CRS interrupt flag clear register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ESYNCC rw	ERRC rw	SYNCWARNC rw	SYNCOKC rw

Toggle Fields.

SYNCOKC

Bit 0: SYNC event OK clear flag.

SYNCWARNC

Bit 1: warning clear flag.

ERRC

Bit 2: Error clear flag.

ESYNCC

Bit 3: Expected SYNC clear flag.

DBGMCU

0xE0042000: Debug support

2/28 fields covered. Toggle Registers.

IDCODE

MCU Device ID Code Register

Offset: 0x0, reset: 0x0, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
REV_ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DEV_ID r

Toggle Fields.

DEV_ID

Bits 0-11: Device Identifier.

REV_ID

Bits 16-31: Revision Identifier.

CR

Debug MCU Configuration Register

Offset: 0x4, reset: 0x0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			TRGOEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRACE_IOEN rw			DBG_STANDBY rw	DBG_STOP rw	DBG_SLEEP rw

Toggle Fields.

DBG_SLEEP

Bit 0: Debug Sleep Mode.

DBG_STOP

Bit 1: Debug Stop Mode.

DBG_STANDBY

Bit 2: Debug Standby Mode.

TRACE_IOEN

Bit 5: Trace port and clock enable.

TRGOEN

Bit 28: External trigger output enable.

APB1FZR1

APB1 Low Freeze Register CPU1

Offset: 0x3C, reset: 0x0, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DBG_LPTIM1_STOP rw								DBG_I2C3_STOP rw		DBG_I2C1_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBG_IWDG_STOP rw	DBG_WWDG_STOP rw	DBG_RTC_STOP rw										DBG_TIMER2_STOP rw

Toggle Fields.

DBG_TIMER2_STOP

Bit 0: Debug Timer 2 stopped when Core is halted.

DBG_RTC_STOP

Bit 10: RTC counter stopped when core is halted.

DBG_WWDG_STOP

Bit 11: WWDG counter stopped when core is halted.

DBG_IWDG_STOP

Bit 12: IWDG counter stopped when core is halted.

DBG_I2C1_STOP

Bit 21: Debug I2C1 SMBUS timeout stopped when Core is halted.

DBG_I2C3_STOP

Bit 23: Debug I2C3 SMBUS timeout stopped when core is halted.

DBG_LPTIM1_STOP

Bit 31: Debug LPTIM1 stopped when Core is halted.

C2AP_B1FZR1

APB1 Low Freeze Register CPU2

Offset: 0x40, reset: 0x0, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DBG_LPTIM1_STOP rw								DBG_I2C3_STOP rw		DBG_I2C1_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBG_IWDG_STOP rw		DBG_RTC_STOP rw										DBG_LPTIM2_STOP rw

Toggle Fields.

DBG_LPTIM2_STOP

Bit 0: LPTIM2 counter stopped when core is halted.

DBG_RTC_STOP

Bit 10: RTC counter stopped when core is halted.

DBG_IWDG_STOP

Bit 12: IWDG stopped when core is halted.

DBG_I2C1_STOP

Bit 21: I2C1 SMBUS timeout stopped when core is halted.

DBG_I2C3_STOP

Bit 23: I2C3 SMBUS timeout stopped when core is halted.

DBG_LPTIM1_STOP

Bit 31: LPTIM1 counter stopped when core is halted.

APB1FZR2

APB1 High Freeze Register CPU1

Offset: 0x44, reset: 0x0, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										DBG_LPTIM2_STOP rw

Toggle Fields.

DBG_LPTIM2_STOP

Bit 5: LPTIM2 counter stopped when core is halted.

C2APB2FZR

APB2 Freeze Register CPU2

Offset: 0x48, reset: 0x0, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_TIM17_STOP rw	DBG_TIM16_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DBG_TIM1_STOP rw

Toggle Fields.

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DBG_TIM17_STOP

Bit 18: TIM17 counter stopped when core is halted.

APB2FZR

APB2 Freeze Register CPU1

Offset: 0x4C, reset: 0x0, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													DBG_TIM17_STOP rw	DBG_TIM16_STOP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				DBG_TIM1_STOP rw

Toggle Fields.

DBG_TIM1_STOP

Bit 11: TIM1 counter stopped when core is halted.

DBG_TIM16_STOP

Bit 17: TIM16 counter stopped when core is halted.

DBG_TIM17_STOP

Bit 18: TIM17 counter stopped when core is halted.

DMA1

0x40020000: Direct memory access controller

28/161 fields covered. Toggle Registers.

ISR

interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TEIF7 r	HTIF7 r	TCIF7 r	GIF7 r	TEIF6 r	HTIF6 r	TCIF6 r	GIF6 r	TEIF5 r	HTIF5 r	TCIF5 r	GIF5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF4 r	HTIF4 r	TCIF4 r	GIF4 r	TEIF3 r	HTIF3 r	TCIF3 r	GIF3 r	TEIF2 r	HTIF2 r	TCIF2 r	GIF2 r	TEIF1 r	HTIF1 r	TCIF1 r	GIF1 r

Toggle Fields.

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

IFCR

interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTEIF7 w	CHTIF7 w	CTCIF7 w	CGIF7 w	CTEIF6 w	CHTIF6 w	CTCIF6 w	CGIF6 w	CTEIF5 w	CHTIF5 w	CTCIF5 w	CGIF5 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF4 w	CHTIF4 w	CTCIF4 w	CGIF4 w	CTEIF3 w	CHTIF3 w	CTCIF3 w	CGIF3 w	CTEIF2 w	CHTIF2 w	CTCIF2 w	CGIF2 w	CTEIF1 w	CHTIF1 w	CTCIF1 w	CGIF1 w

Toggle Fields.

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CCR1

channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR1

channel x number of data register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR1

channel x peripheral address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR2

channel x configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR2

channel x number of data register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR2

channel x peripheral address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR3

channel x configuration register

Offset: 0x30, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR3

channel x number of data register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR3

channel x peripheral address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR3

channel x memory address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR4

channel x configuration register

Offset: 0x44, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR4

channel x number of data register

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR4

channel x peripheral address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR5

channel x configuration register

Offset: 0x58, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR5

channel x number of data register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR5

channel x peripheral address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR6

channel x configuration register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR6

channel x number of data register

Offset: 0x70, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR6

channel x peripheral address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR7

channel x configuration register

Offset: 0x80, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR7

channel x number of data register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR7

channel x peripheral address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR7

channel x memory address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

DMA2

0x40020400: Direct memory access controller

28/168 fields covered. Toggle Registers.

ISR

interrupt status register

Offset: 0x0, reset: 0x00000000, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TEIF7 r	HTIF7 r	TCIF7 r	GIF7 r	TEIF6 r	HTIF6 r	TCIF6 r	GIF6 r	TEIF5 r	HTIF5 r	TCIF5 r	GIF5 r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TEIF4 r	HTIF4 r	TCIF4 r	GIF4 r	TEIF3 r	HTIF3 r	TCIF3 r	GIF3 r	TEIF2 r	HTIF2 r	TCIF2 r	GIF2 r	TEIF1 r	HTIF1 r	TCIF1 r	GIF1 r

Toggle Fields.

GIF1

Bit 0: Channel x global interrupt flag (x = 1 ..7).

TCIF1

Bit 1: Channel x transfer complete flag (x = 1 ..7).

HTIF1

Bit 2: Channel x half transfer flag (x = 1 ..7).

TEIF1

Bit 3: Channel x transfer error flag (x = 1 ..7).

GIF2

Bit 4: Channel x global interrupt flag (x = 1 ..7).

TCIF2

Bit 5: Channel x transfer complete flag (x = 1 ..7).

HTIF2

Bit 6: Channel x half transfer flag (x = 1 ..7).

TEIF2

Bit 7: Channel x transfer error flag (x = 1 ..7).

GIF3

Bit 8: Channel x global interrupt flag (x = 1 ..7).

TCIF3

Bit 9: Channel x transfer complete flag (x = 1 ..7).

HTIF3

Bit 10: Channel x half transfer flag (x = 1 ..7).

TEIF3

Bit 11: Channel x transfer error flag (x = 1 ..7).

GIF4

Bit 12: Channel x global interrupt flag (x = 1 ..7).

TCIF4

Bit 13: Channel x transfer complete flag (x = 1 ..7).

HTIF4

Bit 14: Channel x half transfer flag (x = 1 ..7).

TEIF4

Bit 15: Channel x transfer error flag (x = 1 ..7).

GIF5

Bit 16: Channel x global interrupt flag (x = 1 ..7).

TCIF5

Bit 17: Channel x transfer complete flag (x = 1 ..7).

HTIF5

Bit 18: Channel x half transfer flag (x = 1 ..7).

TEIF5

Bit 19: Channel x transfer error flag (x = 1 ..7).

GIF6

Bit 20: Channel x global interrupt flag (x = 1 ..7).

TCIF6

Bit 21: Channel x transfer complete flag (x = 1 ..7).

HTIF6

Bit 22: Channel x half transfer flag (x = 1 ..7).

TEIF6

Bit 23: Channel x transfer error flag (x = 1 ..7).

GIF7

Bit 24: Channel x global interrupt flag (x = 1 ..7).

TCIF7

Bit 25: Channel x transfer complete flag (x = 1 ..7).

HTIF7

Bit 26: Channel x half transfer flag (x = 1 ..7).

TEIF7

Bit 27: Channel x transfer error flag (x = 1 ..7).

IFCR

interrupt flag clear register

Offset: 0x4, reset: 0x00000000, access: write-only

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				CTEIF7 w	CHTIF7 w	CTCIF7 w	CGIF7 w	CTEIF6 w	CHTIF6 w	CTCIF6 w	CGIF6 w	CTEIF5 w	CHTIF5 w	CTCIF5 w	CGIF5 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTEIF4 w	CHTIF4 w	CTCIF4 w	CGIF4 w	CTEIF3 w	CHTIF3 w	CTCIF3 w	CGIF3 w	CTEIF2 w	CHTIF2 w	CTCIF2 w	CGIF2 w	CTEIF1 w	CHTIF1 w	CTCIF1 w	CGIF1 w

Toggle Fields.

CGIF1

Bit 0: Channel x global interrupt clear (x = 1 ..7).

CTCIF1

Bit 1: Channel x transfer complete clear (x = 1 ..7).

CHTIF1

Bit 2: Channel x half transfer clear (x = 1 ..7).

CTEIF1

Bit 3: Channel x transfer error clear (x = 1 ..7).

CGIF2

Bit 4: Channel x global interrupt clear (x = 1 ..7).

CTCIF2

Bit 5: Channel x transfer complete clear (x = 1 ..7).

CHTIF2

Bit 6: Channel x half transfer clear (x = 1 ..7).

CTEIF2

Bit 7: Channel x transfer error clear (x = 1 ..7).

CGIF3

Bit 8: Channel x global interrupt clear (x = 1 ..7).

CTCIF3

Bit 9: Channel x transfer complete clear (x = 1 ..7).

CHTIF3

Bit 10: Channel x half transfer clear (x = 1 ..7).

CTEIF3

Bit 11: Channel x transfer error clear (x = 1 ..7).

CGIF4

Bit 12: Channel x global interrupt clear (x = 1 ..7).

CTCIF4

Bit 13: Channel x transfer complete clear (x = 1 ..7).

CHTIF4

Bit 14: Channel x half transfer clear (x = 1 ..7).

CTEIF4

Bit 15: Channel x transfer error clear (x = 1 ..7).

CGIF5

Bit 16: Channel x global interrupt clear (x = 1 ..7).

CTCIF5

Bit 17: Channel x transfer complete clear (x = 1 ..7).

CHTIF5

Bit 18: Channel x half transfer clear (x = 1 ..7).

CTEIF5

Bit 19: Channel x transfer error clear (x = 1 ..7).

CGIF6

Bit 20: Channel x global interrupt clear (x = 1 ..7).

CTCIF6

Bit 21: Channel x transfer complete clear (x = 1 ..7).

CHTIF6

Bit 22: Channel x half transfer clear (x = 1 ..7).

CTEIF6

Bit 23: Channel x transfer error clear (x = 1 ..7).

CGIF7

Bit 24: Channel x global interrupt clear (x = 1 ..7).

CTCIF7

Bit 25: Channel x transfer complete clear (x = 1 ..7).

CHTIF7

Bit 26: Channel x half transfer clear (x = 1 ..7).

CTEIF7

Bit 27: Channel x transfer error clear (x = 1 ..7).

CCR1

channel x configuration register

Offset: 0x8, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR1

channel x number of data register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR1

channel x peripheral address register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR1

channel x memory address register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR2

channel x configuration register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR2

channel x number of data register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR2

channel x peripheral address register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR2

channel x memory address register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR3

channel x configuration register

Offset: 0x30, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR3

channel x number of data register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR3

channel x peripheral address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR3

channel x memory address register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR4

channel x configuration register

Offset: 0x44, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR4

channel x number of data register

Offset: 0x48, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR4

channel x peripheral address register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR4

channel x memory address register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR5

channel x configuration register

Offset: 0x58, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR5

channel x number of data register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR5

channel x peripheral address register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR5

channel x memory address register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR6

channel x configuration register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR6

channel x number of data register

Offset: 0x70, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR6

channel x peripheral address register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR6

channel x memory address register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CCR7

channel x configuration register

Offset: 0x80, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MEM2MEM rw	PL rw		MSIZE rw		PSIZE rw		MINC rw	PINC rw	CIRC rw	DIR rw	TEIE rw	HTIE rw	TCIE rw	EN rw

Toggle Fields.

EN

Bit 0: Channel enable.

TCIE

Bit 1: Transfer complete interrupt enable.

HTIE

Bit 2: Half transfer interrupt enable.

TEIE

Bit 3: Transfer error interrupt enable.

DIR

Bit 4: Data transfer direction.

CIRC

Bit 5: Circular mode.

PINC

Bit 6: Peripheral increment mode.

MINC

Bit 7: Memory increment mode.

PSIZE

Bits 8-9: Peripheral size.

MSIZE

Bits 10-11: Memory size.

PL

Bits 12-13: Channel priority level.

MEM2MEM

Bit 14: Memory to memory mode.

CNDTR7

channel x number of data register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NDT rw

Toggle Fields.

NDT

Bits 0-15: Number of data to transfer.

CPAR7

channel x peripheral address register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PA rw

Toggle Fields.

PA

Bits 0-31: Peripheral address.

CMAR7

channel x memory address register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MA rw

Toggle Fields.

MA

Bits 0-31: Memory address.

CSELR

channel selection register

Offset: 0xA8, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				C7S rw				C6S rw				C5S rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C4S rw				C3S rw				C2S rw				C1S rw

Toggle Fields.

C1S

Bits 0-3: DMA channel 1 selection.

C2S

Bits 4-7: DMA channel 2 selection.

C3S

Bits 8-11: DMA channel 3 selection.

C4S

Bits 12-15: DMA channel 4 selection.

C5S

Bits 16-19: DMA channel 5 selection.

C6S

Bits 20-23: DMA channel 6 selection.

C7S

Bits 24-27: DMA channel 7 selection.

DMAMUX1

0x40020800: Direct memory access Multiplexer

22/154 fields covered. Toggle Registers.

C0CR

DMA Multiplexer Channel 0 Control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C1CR

DMA Multiplexer Channel 1 Control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C2CR

DMA Multiplexer Channel 2 Control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C3CR

DMA Multiplexer Channel 3 Control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C4CR

DMA Multiplexer Channel 4 Control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C5CR

DMA Multiplexer Channel 5 Control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C6CR

DMA Multiplexer Channel 6 Control register

Offset: 0x18, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C7CR

DMA Multiplexer Channel 7 Control register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C8CR

DMA Multiplexer Channel 8 Control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C9CR

DMA Multiplexer Channel 9 Control register

Offset: 0x24, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C10CR

DMA Multiplexer Channel 10 Control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C11CR

DMA Multiplexer Channel 11 Control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C12CR

DMA Multiplexer Channel 12 Control register

Offset: 0x30, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

C13CR

DMA Multiplexer Channel 13 Control register

Offset: 0x34, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			SYNC_ID rw					NBREQ rw					SPOL rw		SE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EGE rw	SOIE rw	DMAREQ_ID rw

Toggle Fields.

DMAREQ_ID

Bits 0-7: DMA Request ID.

SOIE

Bit 8: Synchronization Overrun Interrupt Enable.

EGE

Bit 9: Event Generation Enable.

SE

Bit 16: Synchronization enable.

SPOL

Bits 17-18: Sync polarity.

NBREQ

Bits 19-23: Nb request.

SYNC_ID

Bits 24-28: SYNC_ID.

CSR

DMA Multiplexer Channel Status register

Offset: 0x80, reset: 0x00000000, access: read-only

14/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SOF13 r	SOF12 r	SOF11 r	SOF10 r	SOF9 r	SOF8 r	SOF7 r	SOF6 r	SOF5 r	SOF4 r	SOF3 r	SOF2 r	SOF1 r	SOF0 r

Toggle Fields.

SOF0

Bit 0: Synchronization Overrun Flag 0.

SOF1

Bit 1: Synchronization Overrun Flag 1.

SOF2

Bit 2: Synchronization Overrun Flag 2.

SOF3

Bit 3: Synchronization Overrun Flag 3.

SOF4

Bit 4: Synchronization Overrun Flag 4.

SOF5

Bit 5: Synchronization Overrun Flag 5.

SOF6

Bit 6: Synchronization Overrun Flag 6.

SOF7

Bit 7: Synchronization Overrun Flag 7.

SOF8

Bit 8: Synchronization Overrun Flag 8.

SOF9

Bit 9: Synchronization Overrun Flag 9.

SOF10

Bit 10: Synchronization Overrun Flag 10.

SOF11

Bit 11: Synchronization Overrun Flag 11.

SOF12

Bit 12: Synchronization Overrun Flag 12.

SOF13

Bit 13: Synchronization Overrun Flag 13.

CFR

DMA Channel Clear Flag Register

Offset: 0x84, reset: 0x00000000, access: write-only

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CSOF13 w	CSOF12 w	CSOF11 w	CSOF10 w	CSOF9 w	CSOF8 w	CSOF7 w	CSOF6 w	CSOF5 w	CSOF4 w	CSOF3 w	CSOF2 w	CSOF1 w	CSOF0 w

Toggle Fields.

CSOF0

Bit 0: Synchronization Clear Overrun Flag 0.

CSOF1

Bit 1: Synchronization Clear Overrun Flag 1.

CSOF2

Bit 2: Synchronization Clear Overrun Flag 2.

CSOF3

Bit 3: Synchronization Clear Overrun Flag 3.

CSOF4

Bit 4: Synchronization Clear Overrun Flag 4.

CSOF5

Bit 5: Synchronization Clear Overrun Flag 5.

CSOF6

Bit 6: Synchronization Clear Overrun Flag 6.

CSOF7

Bit 7: Synchronization Clear Overrun Flag 7.

CSOF8

Bit 8: Synchronization Clear Overrun Flag 8.

CSOF9

Bit 9: Synchronization Clear Overrun Flag 9.

CSOF10

Bit 10: Synchronization Clear Overrun Flag 10.

CSOF11

Bit 11: Synchronization Clear Overrun Flag 11.

CSOF12

Bit 12: Synchronization Clear Overrun Flag 12.

CSOF13

Bit 13: Synchronization Clear Overrun Flag 13.

RG0CR

DMA Request Generator 0 Control Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle Fields.

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RG1CR

DMA Request Generator 1 Control Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle Fields.

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RG2CR

DMA Request Generator 2 Control Register

Offset: 0x108, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle Fields.

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RG3CR

DMA Request Generator 3 Control Register

Offset: 0x10C, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								GNBREQ rw					GPOL rw		GE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							OIE rw				SIG_ID rw

Toggle Fields.

SIG_ID

Bits 0-4: Signal ID.

OIE

Bit 8: Overrun Interrupt Enable.

GE

Bit 16: Generation Enable.

GPOL

Bits 17-18: Generation Polarity.

GNBREQ

Bits 19-23: Number of Request.

RGSR

DMA Request Generator Status Register

Offset: 0x140, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												OF3 r	OF2 r	OF1 r	OF0 r

Toggle Fields.

OF0

Bit 0: Generator Overrun Flag 0.

OF1

Bit 1: Generator Overrun Flag 1.

OF2

Bit 2: Generator Overrun Flag 2.

OF3

Bit 3: Generator Overrun Flag 3.

RGCFR

DMA Request Generator Clear Flag Register

Offset: 0x144, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CSOF3 r	CSOF2 r	CSOF1 r	CSOF0 r

Toggle Fields.

CSOF0

Bit 0: Generator Clear Overrun Flag 0.

CSOF1

Bit 1: Generator Clear Overrun Flag 1.

CSOF2

Bit 2: Generator Clear Overrun Flag 2.

CSOF3

Bit 3: Generator Clear Overrun Flag 3.

EXTI

0x58000800: External interrupt/event controller

13/39 fields covered. Toggle Registers.

RTSR1

rising trigger selection register

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RT_31 rw										RT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RT rw

Toggle Fields.

RT

Bits 0-21: Rising trigger event configuration bit of Configurable Event input.

RT_31

Bit 31: Rising trigger event configuration bit of Configurable Event input.

FTSR1

falling trigger selection register

Offset: 0x4, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FT_31 rw										FT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
FT rw

Toggle Fields.

FT

Bits 0-21: Falling trigger event configuration bit of Configurable Event input.

FT_31

Bit 31: Falling trigger event configuration bit of Configurable Event input.

SWIER1

software interrupt event register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SWI_31 rw										SWI rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWI rw

Toggle Fields.

SWI

Bits 0-21: Software interrupt on event.

SWI_31

Bit 31: Software interrupt on event.

PR1

EXTI pending register

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PIF_31 rw										PIF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PIF rw

Toggle Fields.

PIF

Bits 0-21: Configurable event inputs Pending bit.

PIF_31

Bit 31: Configurable event inputs Pending bit.

RTSR2

rising trigger selection register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						RT40_41 rw								RT33 rw

Toggle Fields.

RT33

Bit 1: Rising trigger event configuration bit of Configurable Event input.

RT40_41

Bits 8-9: Rising trigger event configuration bit of Configurable Event input.

FTSR2

falling trigger selection register

Offset: 0x24, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						FT40_41 rw								FT33 rw

Toggle Fields.

FT33

Bit 1: Falling trigger event configuration bit of Configurable Event input.

FT40_41

Bits 8-9: Falling trigger event configuration bit of Configurable Event input.

SWIER2

software interrupt event register

Offset: 0x28, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						SWI40_41 rw								SWI33 rw

Toggle Fields.

SWI33

Bit 1: Software interrupt on event.

SWI40_41

Bits 8-9: Software interrupt on event.

PR2

pending register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PIF40_41 rw								PIF33 rw

Toggle Fields.

PIF33

Bit 1: Configurable event inputs x+32 Pending bit..

PIF40_41

Bits 8-9: Configurable event inputs x+32 Pending bit..

C1IMR1

CPUm wakeup with interrupt mask register

Offset: 0x80, reset: 0x7FC00000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM rw

Toggle Fields.

IM

Bits 0-31: CPU(m) wakeup with interrupt Mask on Event input.

C1EMR1

CPUm wakeup with event mask register

Offset: 0x84, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										EM17_21 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM0_15 rw

Toggle Fields.

EM0_15

Bits 0-15: CPU(m) Wakeup with event generation Mask on Event input.

EM17_21

Bits 17-21: CPU(m) Wakeup with event generation Mask on Event input.

C1IMR2

CPUm wakeup with interrupt mask register

Offset: 0x90, reset: 0x0001FCFD, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM rw

Toggle Fields.

IM

Bits 0-16: CPUm Wakeup with interrupt Mask on Event input.

C1EMR2

CPUm wakeup with event mask register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EM rw

Toggle Fields.

EM

Bits 8-9: CPU(m) Wakeup with event generation Mask on Event input.

C2IMR1

CPUm wakeup with interrupt mask register

Offset: 0xC0, reset: 0x7FC00000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM rw

Toggle Fields.

IM

Bits 0-31: CPU(m) wakeup with interrupt Mask on Event input.

C2EMR1

CPUm wakeup with event mask register

Offset: 0xC4, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										EM17_21 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EM0_15 rw

Toggle Fields.

EM0_15

Bits 0-15: CPU(m) Wakeup with event generation Mask on Event input.

EM17_21

Bits 17-21: CPU(m) Wakeup with event generation Mask on Event input.

C2IMR2

CPUm wakeup with interrupt mask register

Offset: 0xD0, reset: 0x0001FCFD, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IM rw

Toggle Fields.

IM

Bits 0-16: CPUm Wakeup with interrupt Mask on Event input.

C2EMR2

CPUm wakeup with event mask register

Offset: 0xD4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						EM rw

Toggle Fields.

EM

Bits 8-9: CPU(m) Wakeup with event generation Mask on Event input.

HWCFGR7

EXTI Hardware configuration registers

Offset: 0x3D8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT r

Toggle Fields.

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR6

Hardware configuration registers

Offset: 0x3DC, reset: 0x00000300, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT r

Toggle Fields.

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR5

Hardware configuration registers

Offset: 0x3E0, reset: 0x003EFFFF, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CPUEVENT r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVENT r

Toggle Fields.

CPUEVENT

Bits 0-31: HW configuration CPU event generation.

HWCFGR4

Hardware configuration registers

Offset: 0x3E4, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG r

Toggle Fields.

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR3

Hardware configuration registers

Offset: 0x3E8, reset: 0x00000302, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG r

Toggle Fields.

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR2

Hardware configuration registers

Offset: 0x3EC, reset: 0x803FFFFF, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EVENT_TRG r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EVENT_TRG r

Toggle Fields.

EVENT_TRG

Bits 0-31: HW configuration event trigger type.

HWCFGR1

Hardware configuration register 1

Offset: 0x3F0, reset: 0x00003130, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CPUEVTEN r				NBCPUS r				NBEVENTS r

Toggle Fields.

NBEVENTS

Bits 0-7: HW configuration number of event.

NBCPUS

Bits 8-11: HW configuration number of CPUs.

CPUEVTEN

Bits 12-15: HW configuration of CPU(m) event output enable.

VERR

EXTI IP Version register

Offset: 0x3F4, reset: 0X00000020, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields.

MINREV

Bits 0-3: Minor Revision number.

MAJREV

Bits 4-7: Major Revision number.

IPIDR

Identification register

Offset: 0x3F8, reset: 0x000E0001, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields.

IPID

Bits 0-31: IP Identification.

SIDR

Size ID register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields.

SID

Bits 0-31: Size Identification.

Flash

0x58004000: Flash

7/105 fields covered. Toggle Registers.

ACR

Access control register

Offset: 0x0, reset: 0x00000600, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															EMPTY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PES rw			DCRST rw	ICRST rw	DCEN rw	ICEN rw	PRFTEN rw						LATENCY rw

Toggle Fields.

LATENCY

Bits 0-2: Latency.

PRFTEN

Bit 8: Prefetch enable.

ICEN

Bit 9: Instruction cache enable.

DCEN

Bit 10: Data cache enable.

ICRST

Bit 11: Instruction cache reset.

DCRST

Bit 12: Data cache reset.

PES

Bit 15: CPU1 CortexM4 program erase suspend request.

EMPTY

Bit 16: Flash User area empty.

KEYR

Flash key register

Offset: 0x8, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEYR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEYR w

Toggle Fields.

KEYR

Bits 0-31: KEYR.

OPTKEYR

Option byte key register

Offset: 0xC, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OPTKEYR w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTKEYR w

Toggle Fields.

OPTKEYR

Bits 0-31: Option byte key.

SR

Status register

Offset: 0x10, reset: 0x00000000, access: Unspecified

4/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												PESD r	CFGBSY r		BSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OPTVERR rw	RDERR rw	OPTNV r				FASTERR rw	MISERR rw	PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

Toggle Fields.

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: Write protected error.

PGAERR

Bit 5: Programming alignment error.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

OPTNV

Bit 13: User Option OPTVAL indication.

RDERR

Bit 14: PCROP read error.

OPTVERR

Bit 15: Option validity error.

BSY

Bit 16: Busy.

CFGBSY

Bit 18: Programming or erase configuration busy.

PESD

Bit 19: Programming or erase operation suspended.

CR

Flash control register

Offset: 0x14, reset: 0xC0000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw	OPTLOCK rw			OBL_LAUNCH rw	RDERRIE rw	ERRIE rw	EOPIE rw						FSTPG rw	OPTSTRT rw	STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					PNB rw								MER rw	PER rw	PG rw

Toggle Fields.

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER

Bit 2: This bit triggers the mass erase (all user pages) when set.

PNB

Bits 3-10: Page number selection.

STRT

Bit 16: Start.

OPTSTRT

Bit 17: Options modification start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: PCROP read error interrupt enable.

OBL_LAUNCH

Bit 27: Force the option byte loading.

OPTLOCK

Bit 30: Options Lock.

LOCK

Bit 31: FLASH_CR Lock.

ECCR

Flash ECC register

Offset: 0x18, reset: 0x00000000, access: Unspecified

3/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ECCD rw	ECCC rw		CPUID r				ECCCIE rw				SYSF_ECC r				ADDR_ECC r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR_ECC r

Toggle Fields.

ADDR_ECC

Bits 0-16: ECC fail address.

SYSF_ECC

Bit 20: System Flash ECC fail.

ECCCIE

Bit 24: ECC correction interrupt enable.

CPUID

Bits 26-28: CPU identification.

ECCC

Bit 30: ECC correction.

ECCD

Bit 31: ECC detection.

OPTR

Flash option register

Offset: 0x20, reset: 0x10708000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AGC_TRIM rw				nBOOT0 rw	nSWBOOT0 rw	SRAM2_RST rw	SRAM2_PE rw	nBOOT1 rw				WWDG_SW rw	IWDG_STDBY rw	IWDG_STOP rw	IDWG_SW rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	nRST_SHDW rw	nRST_STDBY rw	nRST_STOP rw	BOR_LEV rw			ESE rw	RDP rw

Toggle Fields.

RDP

Bits 0-7: Read protection level.

ESE

Bit 8: Security enabled.

BOR_LEV

Bits 9-11: BOR reset Level.

nRST_STOP

Bit 12: nRST_STOP.

nRST_STDBY

Bit 13: nRST_STDBY.

nRST_SHDW

Bit 14: nRST_SHDW.

IDWG_SW

Bit 16: Independent watchdog selection.

IWDG_STOP

Bit 17: Independent watchdog counter freeze in Stop mode.

IWDG_STDBY

Bit 18: Independent watchdog counter freeze in Standby mode.

WWDG_SW

Bit 19: Window watchdog selection.

nBOOT1

Bit 23: Boot configuration.

SRAM2_PE

Bit 24: SRAM2 parity check enable.

SRAM2_RST

Bit 25: SRAM2 Erase when system reset.

nSWBOOT0

Bit 26: Software Boot0.

nBOOT0

Bit 27: nBoot0 option bit.

AGC_TRIM

Bits 29-31: Radio Automatic Gain Control Trimming.

PCROP1ASR

Flash Bank 1 PCROP Start address zone A register

Offset: 0x24, reset: 0xFFFFFE00, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PCROP1A_STRT rw

Toggle Fields.

PCROP1A_STRT

Bits 0-8: Bank 1 PCROPQ area start offset.

PCROP1AER

Flash Bank 1 PCROP End address zone A register

Offset: 0x28, reset: 0x7FFFFE00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PCROP_RDP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PCROP1A_END rw

Toggle Fields.

PCROP1A_END

Bits 0-8: Bank 1 PCROP area end offset.

PCROP_RDP

Bit 31: PCROP area preserved when RDP level decreased.

WRP1AR

Flash Bank 1 WRP area A address register

Offset: 0x2C, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								WRP1A_END rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WRP1A_STRT rw

Toggle Fields.

WRP1A_STRT

Bits 0-7: Bank 1 WRP first area A start offset.

WRP1A_END

Bits 16-23: Bank 1 WRP first area A end offset.

WRP1BR

Flash Bank 1 WRP area B address register

Offset: 0x30, reset: 0xFF00FF00, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								WRP1B_STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WRP1B_END rw

Toggle Fields.

WRP1B_END

Bits 0-7: Bank 1 WRP second area B start offset.

WRP1B_STRT

Bits 16-23: Bank 1 WRP second area B end offset.

PCROP1BSR

Flash Bank 1 PCROP Start address area B register

Offset: 0x34, reset: 0xFFFFFE00, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PCROP1B_STRT rw

Toggle Fields.

PCROP1B_STRT

Bits 0-8: Bank 1 PCROP area B start offset.

PCROP1BER

Flash Bank 1 PCROP End address area B register

Offset: 0x38, reset: 0xFFFFFE00, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							PCROP1B_END rw

Toggle Fields.

PCROP1B_END

Bits 0-8: Bank 1 PCROP area end area B offset.

IPCCBR

IPCC mailbox data buffer address register

Offset: 0x3C, reset: 0xFFFFC000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		IPCCDBA rw

Toggle Fields.

IPCCDBA

Bits 0-13: PCC mailbox data buffer base address.

C2ACR

CPU2 cortex M0 access control register

Offset: 0x5C, reset: 0x00000600, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PES rw				ICRST rw		ICEN rw	PRFTEN rw

Toggle Fields.

PRFTEN

Bit 8: CPU2 cortex M0 prefetch enable.

ICEN

Bit 9: CPU2 cortex M0 instruction cache enable.

ICRST

Bit 11: CPU2 cortex M0 instruction cache reset.

PES

Bit 15: CPU2 cortex M0 program erase suspend request.

C2SR

CPU2 cortex M0 status register

Offset: 0x60, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												PESD rw	CFGBSY rw		BSY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	RDERR rw					FASTERR rw	MISSERR rw	PGSERR rw	SIZERR rw	PGAERR rw	WRPERR rw	PROGERR rw		OPERR rw	EOP rw

Toggle Fields.

EOP

Bit 0: End of operation.

OPERR

Bit 1: Operation error.

PROGERR

Bit 3: Programming error.

WRPERR

Bit 4: write protection error.

PGAERR

Bit 5: Programming alignment error.

SIZERR

Bit 6: Size error.

PGSERR

Bit 7: Programming sequence error.

MISSERR

Bit 8: Fast programming data miss error.

FASTERR

Bit 9: Fast programming error.

RDERR

Bit 14: PCROP read error.

BSY

Bit 16: Busy.

CFGBSY

Bit 18: Programming or erase configuration busy.

PESD

Bit 19: Programming or erase operation suspended.

C2CR

CPU2 cortex M0 control register

Offset: 0x64, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					RDERRIE rw	ERRIE rw	EOPIE rw						FSTPG rw		STRT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					PNB rw								MER rw	PER rw	PG rw

Toggle Fields.

PG

Bit 0: Programming.

PER

Bit 1: Page erase.

MER

Bit 2: Masse erase.

PNB

Bits 3-10: Page Number selection.

STRT

Bit 16: Start.

FSTPG

Bit 18: Fast programming.

EOPIE

Bit 24: End of operation interrupt enable.

ERRIE

Bit 25: Error interrupt enable.

RDERRIE

Bit 26: PCROP read error interrupt enable.

SFR

Secure flash start address register

Offset: 0x80, reset: 0xFFFFEE00, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DDS rw				FSD rw	SFSA rw

Toggle Fields.

SFSA

Bits 0-7: Secure flash start address.

FSD

Bit 8: Flash security disable.

DDS

Bit 12: Disable Cortex M0 debug access.

SRRVR

Secure SRAM2 start address and cortex M0 reset vector register

Offset: 0x84, reset: 0x01000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
C2OPT rw	NBRSD rw	SNBRSA rw						BRSD rw	SBRSA rw					SBRV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SBRV rw

Toggle Fields.

SBRV

Bits 0-17: cortex M0 access control register.

SBRSA

Bits 18-22: Secure backup SRAM2a start address.

BRSD

Bit 23: backup SRAM2a security disable.

SNBRSA

Bits 25-29: Secure non backup SRAM2a start address.

NBRSD

Bit 30: non-backup SRAM2b security disable.

C2OPT

Bit 31: CPU2 cortex M0 boot reset vector memory selection.

FPU

0xE000EF34: Floting point unit

0/24 fields covered. Toggle Registers.

FPCCR

Floating-point context control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ASPEN rw	LSPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							MONRDY rw		BFRDY rw	MMRDY rw	HFRDY rw	THREAD rw		USER rw	LSPACT rw

Toggle Fields.

LSPACT

Bit 0: LSPACT.

USER

Bit 1: USER.

THREAD

Bit 3: THREAD.

HFRDY

Bit 4: HFRDY.

MMRDY

Bit 5: MMRDY.

BFRDY

Bit 6: BFRDY.

MONRDY

Bit 8: MONRDY.

LSPEN

Bit 30: LSPEN.

ASPEN

Bit 31: ASPEN.

FPCAR

Floating-point context address register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDRESS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS rw

Toggle Fields.

ADDRESS

Bits 3-31: Location of unpopulated floating-point.

FPSCR

Floating-point status control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
N rw	Z rw	C rw	V rw		AHP rw	DN rw	FZ rw	RMode rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IDC rw			IXC rw	UFC rw	OFC rw	DZC rw	IOC rw

Toggle Fields.

IOC

Bit 0: Invalid operation cumulative exception bit.

DZC

Bit 1: Division by zero cumulative exception bit..

OFC

Bit 2: Overflow cumulative exception bit.

UFC

Bit 3: Underflow cumulative exception bit.

IXC

Bit 4: Inexact cumulative exception bit.

IDC

Bit 7: Input denormal cumulative exception bit..

RMode

Bits 22-23: Rounding Mode control field.

FZ

Bit 24: Flush-to-zero mode control bit:.

DN

Bit 25: Default NaN mode control bit.

AHP

Bit 26: Alternative half-precision control bit.

V

Bit 28: Overflow condition code flag.

C

Bit 29: Carry condition code flag.

Z

Bit 30: Zero condition code flag.

N

Bit 31: Negative condition code flag.

FPU_CPACR

0xE000ED88: Floating point unit CPACR

0/1 fields covered. Toggle Registers.

CPACR

Coprocessor access control register

Offset: 0x0, reset: 0x0000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

CP

Bits 20-23: CP.

GPIOA

0x48000000: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xABFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x0C000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x64000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOB

0x48000400: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFEBF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x000000C0, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000100, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOC

0x48000800: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x000000C0, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000100, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOD

0x48000C00: General-purpose I/Os

16/177 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0xFFFFFFFF, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MODER15 rw		MODER14 rw		MODER13 rw		MODER12 rw		MODER11 rw		MODER10 rw		MODER9 rw		MODER8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MODER7 rw		MODER6 rw		MODER5 rw		MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

MODER5

Bits 10-11: Port x configuration bits (y = 0..15).

MODER6

Bits 12-13: Port x configuration bits (y = 0..15).

MODER7

Bits 14-15: Port x configuration bits (y = 0..15).

MODER8

Bits 16-17: Port x configuration bits (y = 0..15).

MODER9

Bits 18-19: Port x configuration bits (y = 0..15).

MODER10

Bits 20-21: Port x configuration bits (y = 0..15).

MODER11

Bits 22-23: Port x configuration bits (y = 0..15).

MODER12

Bits 24-25: Port x configuration bits (y = 0..15).

MODER13

Bits 26-27: Port x configuration bits (y = 0..15).

MODER14

Bits 28-29: Port x configuration bits (y = 0..15).

MODER15

Bits 30-31: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OT15 rw	OT14 rw	OT13 rw	OT12 rw	OT11 rw	OT10 rw	OT9 rw	OT8 rw	OT7 rw	OT6 rw	OT5 rw	OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OT5

Bit 5: Port x configuration bits (y = 0..15).

OT6

Bit 6: Port x configuration bits (y = 0..15).

OT7

Bit 7: Port x configuration bits (y = 0..15).

OT8

Bit 8: Port x configuration bits (y = 0..15).

OT9

Bit 9: Port x configuration bits (y = 0..15).

OT10

Bit 10: Port x configuration bits (y = 0..15).

OT11

Bit 11: Port x configuration bits (y = 0..15).

OT12

Bit 12: Port x configuration bits (y = 0..15).

OT13

Bit 13: Port x configuration bits (y = 0..15).

OT14

Bit 14: Port x configuration bits (y = 0..15).

OT15

Bit 15: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x000000C0, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
OSPEEDR15 rw		OSPEEDR14 rw		OSPEEDR13 rw		OSPEEDR12 rw		OSPEEDR11 rw		OSPEEDR10 rw		OSPEEDR9 rw		OSPEEDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OSPEEDR7 rw		OSPEEDR6 rw		OSPEEDR5 rw		OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

OSPEEDR5

Bits 10-11: Port x configuration bits (y = 0..15).

OSPEEDR6

Bits 12-13: Port x configuration bits (y = 0..15).

OSPEEDR7

Bits 14-15: Port x configuration bits (y = 0..15).

OSPEEDR8

Bits 16-17: Port x configuration bits (y = 0..15).

OSPEEDR9

Bits 18-19: Port x configuration bits (y = 0..15).

OSPEEDR10

Bits 20-21: Port x configuration bits (y = 0..15).

OSPEEDR11

Bits 22-23: Port x configuration bits (y = 0..15).

OSPEEDR12

Bits 24-25: Port x configuration bits (y = 0..15).

OSPEEDR13

Bits 26-27: Port x configuration bits (y = 0..15).

OSPEEDR14

Bits 28-29: Port x configuration bits (y = 0..15).

OSPEEDR15

Bits 30-31: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000100, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PUPDR15 rw		PUPDR14 rw		PUPDR13 rw		PUPDR12 rw		PUPDR11 rw		PUPDR10 rw		PUPDR9 rw		PUPDR8 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PUPDR7 rw		PUPDR6 rw		PUPDR5 rw		PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR5

Bits 10-11: Port x configuration bits (y = 0..15).

PUPDR6

Bits 12-13: Port x configuration bits (y = 0..15).

PUPDR7

Bits 14-15: Port x configuration bits (y = 0..15).

PUPDR8

Bits 16-17: Port x configuration bits (y = 0..15).

PUPDR9

Bits 18-19: Port x configuration bits (y = 0..15).

PUPDR10

Bits 20-21: Port x configuration bits (y = 0..15).

PUPDR11

Bits 22-23: Port x configuration bits (y = 0..15).

PUPDR12

Bits 24-25: Port x configuration bits (y = 0..15).

PUPDR13

Bits 26-27: Port x configuration bits (y = 0..15).

PUPDR14

Bits 28-29: Port x configuration bits (y = 0..15).

PUPDR15

Bits 30-31: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

16/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IDR15 r	IDR14 r	IDR13 r	IDR12 r	IDR11 r	IDR10 r	IDR9 r	IDR8 r	IDR7 r	IDR6 r	IDR5 r	IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

IDR5

Bit 5: Port input data (y = 0..15).

IDR6

Bit 6: Port input data (y = 0..15).

IDR7

Bit 7: Port input data (y = 0..15).

IDR8

Bit 8: Port input data (y = 0..15).

IDR9

Bit 9: Port input data (y = 0..15).

IDR10

Bit 10: Port input data (y = 0..15).

IDR11

Bit 11: Port input data (y = 0..15).

IDR12

Bit 12: Port input data (y = 0..15).

IDR13

Bit 13: Port input data (y = 0..15).

IDR14

Bit 14: Port input data (y = 0..15).

IDR15

Bit 15: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ODR15 rw	ODR14 rw	ODR13 rw	ODR12 rw	ODR11 rw	ODR10 rw	ODR9 rw	ODR8 rw	ODR7 rw	ODR6 rw	ODR5 rw	ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

ODR5

Bit 5: Port output data (y = 0..15).

ODR6

Bit 6: Port output data (y = 0..15).

ODR7

Bit 7: Port output data (y = 0..15).

ODR8

Bit 8: Port output data (y = 0..15).

ODR9

Bit 9: Port output data (y = 0..15).

ODR10

Bit 10: Port output data (y = 0..15).

ODR11

Bit 11: Port output data (y = 0..15).

ODR12

Bit 12: Port output data (y = 0..15).

ODR13

Bit 13: Port output data (y = 0..15).

ODR14

Bit 14: Port output data (y = 0..15).

ODR15

Bit 15: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BS15 w	BS14 w	BS13 w	BS12 w	BS11 w	BS10 w	BS9 w	BS8 w	BS7 w	BS6 w	BS5 w	BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BS5

Bit 5: Port x set bit y (y= 0..15).

BS6

Bit 6: Port x set bit y (y= 0..15).

BS7

Bit 7: Port x set bit y (y= 0..15).

BS8

Bit 8: Port x set bit y (y= 0..15).

BS9

Bit 9: Port x set bit y (y= 0..15).

BS10

Bit 10: Port x set bit y (y= 0..15).

BS11

Bit 11: Port x set bit y (y= 0..15).

BS12

Bit 12: Port x set bit y (y= 0..15).

BS13

Bit 13: Port x set bit y (y= 0..15).

BS14

Bit 14: Port x set bit y (y= 0..15).

BS15

Bit 15: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

BR5

Bit 21: Port x reset bit y (y = 0..15).

BR6

Bit 22: Port x reset bit y (y = 0..15).

BR7

Bit 23: Port x reset bit y (y = 0..15).

BR8

Bit 24: Port x reset bit y (y = 0..15).

BR9

Bit 25: Port x reset bit y (y = 0..15).

BR10

Bit 26: Port x reset bit y (y = 0..15).

BR11

Bit 27: Port x reset bit y (y = 0..15).

BR12

Bit 28: Port x reset bit y (y = 0..15).

BR13

Bit 29: Port x reset bit y (y = 0..15).

BR14

Bit 30: Port x reset bit y (y = 0..15).

BR15

Bit 31: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
LCK15 rw	LCK14 rw	LCK13 rw	LCK12 rw	LCK11 rw	LCK10 rw	LCK9 rw	LCK8 rw	LCK7 rw	LCK6 rw	LCK5 rw	LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCK5

Bit 5: Port x lock bit y (y= 0..15).

LCK6

Bit 6: Port x lock bit y (y= 0..15).

LCK7

Bit 7: Port x lock bit y (y= 0..15).

LCK8

Bit 8: Port x lock bit y (y= 0..15).

LCK9

Bit 9: Port x lock bit y (y= 0..15).

LCK10

Bit 10: Port x lock bit y (y= 0..15).

LCK11

Bit 11: Port x lock bit y (y= 0..15).

LCK12

Bit 12: Port x lock bit y (y= 0..15).

LCK13

Bit 13: Port x lock bit y (y= 0..15).

LCK14

Bit 14: Port x lock bit y (y= 0..15).

LCK15

Bit 15: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL7 rw				AFSEL6 rw				AFSEL5 rw				AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFSEL5

Bits 20-23: Alternate function selection for port x bit y (y = 0..7).

AFSEL6

Bits 24-27: Alternate function selection for port x bit y (y = 0..7).

AFSEL7

Bits 28-31: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BR15 w	BR14 w	BR13 w	BR12 w	BR11 w	BR10 w	BR9 w	BR8 w	BR7 w	BR6 w	BR5 w	BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

BR5

Bit 5: Port Reset bit.

BR6

Bit 6: Port Reset bit.

BR7

Bit 7: Port Reset bit.

BR8

Bit 8: Port Reset bit.

BR9

Bit 9: Port Reset bit.

BR10

Bit 10: Port Reset bit.

BR11

Bit 11: Port Reset bit.

BR12

Bit 12: Port Reset bit.

BR13

Bit 13: Port Reset bit.

BR14

Bit 14: Port Reset bit.

BR15

Bit 15: Port Reset bit.

GPIOE

0x48001000: General-purpose I/Os

5/64 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x000003FF, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						MODER4 rw		MODER3 rw		MODER2 rw		MODER1 rw		MODER0 rw

Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER2

Bits 4-5: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

MODER4

Bits 8-9: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											OT4 rw	OT3 rw	OT2 rw	OT1 rw	OT0 rw

Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT2

Bit 2: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OT4

Bit 4: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x000000C0, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OSPEEDR4 rw		OSPEEDR3 rw		OSPEEDR2 rw		OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR2

Bits 4-5: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

OSPEEDR4

Bits 8-9: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						PUPDR4 rw		PUPDR3 rw		PUPDR2 rw		PUPDR1 rw		PUPDR0 rw

Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR2

Bits 4-5: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR4

Bits 8-9: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											IDR4 r	IDR3 r	IDR2 r	IDR1 r	IDR0 r

Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR2

Bit 2: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

IDR4

Bit 4: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											ODR4 rw	ODR3 rw	ODR2 rw	ODR1 rw	ODR0 rw

Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR2

Bit 2: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

ODR4

Bit 4: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											BR4 w	BR3 w	BR2 w	BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BS4 w	BS3 w	BS2 w	BS1 w	BS0 w

Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS2

Bit 2: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BS4

Bit 4: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR2

Bit 18: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

BR4

Bit 20: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											LCK4 rw	LCK3 rw	LCK2 rw	LCK1 rw	LCK0 rw

Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK2

Bit 2: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCK4

Bit 4: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												AFSEL4 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw				AFSEL2 rw				AFSEL1 rw				AFSEL0 rw

Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL2

Bits 8-11: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFSEL4

Bits 16-19: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											BR4 w	BR3 w	BR2 w	BR1 w	BR0 w

Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR2

Bit 2: Port Reset bit.

BR3

Bit 3: Port Reset bit.

BR4

Bit 4: Port Reset bit.

GPIOH

0x48001C00: General-purpose I/Os

3/42 fields covered. Toggle Registers.

MODER

GPIO port mode register

Offset: 0x0, reset: 0x000000CF, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MODER3 rw				MODER1 rw		MODER0 rw

Toggle Fields.

MODER0

Bits 0-1: Port x configuration bits (y = 0..15).

MODER1

Bits 2-3: Port x configuration bits (y = 0..15).

MODER3

Bits 6-7: Port x configuration bits (y = 0..15).

OTYPER

GPIO port output type register

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												OT3 rw		OT1 rw	OT0 rw

Toggle Fields.

OT0

Bit 0: Port x configuration bits (y = 0..15).

OT1

Bit 1: Port x configuration bits (y = 0..15).

OT3

Bit 3: Port x configuration bits (y = 0..15).

OSPEEDR

GPIO port output speed register

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								OSPEEDR3 rw				OSPEEDR1 rw		OSPEEDR0 rw

Toggle Fields.

OSPEEDR0

Bits 0-1: Port x configuration bits (y = 0..15).

OSPEEDR1

Bits 2-3: Port x configuration bits (y = 0..15).

OSPEEDR3

Bits 6-7: Port x configuration bits (y = 0..15).

PUPDR

GPIO port pull-up/pull-down register

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PUPDR3 rw				PUPDR1 rw		PUPDR0 rw

Toggle Fields.

PUPDR0

Bits 0-1: Port x configuration bits (y = 0..15).

PUPDR1

Bits 2-3: Port x configuration bits (y = 0..15).

PUPDR3

Bits 6-7: Port x configuration bits (y = 0..15).

IDR

GPIO port input data register

Offset: 0x10, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												IDR3 r		IDR1 r	IDR0 r

Toggle Fields.

IDR0

Bit 0: Port input data (y = 0..15).

IDR1

Bit 1: Port input data (y = 0..15).

IDR3

Bit 3: Port input data (y = 0..15).

ODR

GPIO port output data register

Offset: 0x14, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												ODR3 rw		ODR1 rw	ODR0 rw

Toggle Fields.

ODR0

Bit 0: Port output data (y = 0..15).

ODR1

Bit 1: Port output data (y = 0..15).

ODR3

Bit 3: Port output data (y = 0..15).

BSRR

GPIO port bit set/reset register

Offset: 0x18, reset: 0x00000000, access: write-only

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BR3 w		BR1 w	BR0 w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BS3 w		BS1 w	BS0 w

Toggle Fields.

BS0

Bit 0: Port x set bit y (y= 0..15).

BS1

Bit 1: Port x set bit y (y= 0..15).

BS3

Bit 3: Port x set bit y (y= 0..15).

BR0

Bit 16: Port x set bit y (y= 0..15).

BR1

Bit 17: Port x reset bit y (y = 0..15).

BR3

Bit 19: Port x reset bit y (y = 0..15).

LCKR

GPIO port configuration lock register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															LCKK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												LCK3 rw		LCK1 rw	LCK0 rw

Toggle Fields.

LCK0

Bit 0: Port x lock bit y (y= 0..15).

LCK1

Bit 1: Port x lock bit y (y= 0..15).

LCK3

Bit 3: Port x lock bit y (y= 0..15).

LCKK

Bit 16: Port x lock bit y (y= 0..15).

AFRL

GPIO alternate function low register

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL3 rw								AFSEL1 rw				AFSEL0 rw

Toggle Fields.

AFSEL0

Bits 0-3: Alternate function selection for port x bit y (y = 0..7).

AFSEL1

Bits 4-7: Alternate function selection for port x bit y (y = 0..7).

AFSEL3

Bits 12-15: Alternate function selection for port x bit y (y = 0..7).

AFRH

GPIO alternate function high register

Offset: 0x24, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
AFSEL15 rw				AFSEL14 rw				AFSEL13 rw				AFSEL12 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
AFSEL11 rw				AFSEL10 rw				AFSEL9 rw				AFSEL8 rw

Toggle Fields.

AFSEL8

Bits 0-3: Alternate function selection for port x bit y (y = 8..15).

AFSEL9

Bits 4-7: Alternate function selection for port x bit y (y = 8..15).

AFSEL10

Bits 8-11: Alternate function selection for port x bit y (y = 8..15).

AFSEL11

Bits 12-15: Alternate function selection for port x bit y (y = 8..15).

AFSEL12

Bits 16-19: Alternate function selection for port x bit y (y = 8..15).

AFSEL13

Bits 20-23: Alternate function selection for port x bit y (y = 8..15).

AFSEL14

Bits 24-27: Alternate function selection for port x bit y (y = 8..15).

AFSEL15

Bits 28-31: Alternate function selection for port x bit y (y = 8..15).

BRR

port bit reset register

Offset: 0x28, reset: 0x00000000, access: write-only

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												BR3 w		BR1 w	BR0 w

Toggle Fields.

BR0

Bit 0: Port Reset bit.

BR1

Bit 1: Port Reset bit.

BR3

Bit 3: Port Reset bit.

HSEM

0x58001400: HSEM

110/213 fields covered. Toggle Registers.

R0

Semaphore 0 register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R1

Semaphore 1 register

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R2

Semaphore 2 register

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R3

Semaphore 3 register

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R4

Semaphore 4 register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R5

Semaphore 5 register

Offset: 0x14, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R6

Semaphore 6 register

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R7

Semaphore 7 register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R8

Semaphore 8 register

Offset: 0x20, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R9

Semaphore 9 register

Offset: 0x24, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R10

Semaphore 10 register

Offset: 0x28, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R11

Semaphore 11 register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R12

Semaphore 12 register

Offset: 0x30, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R13

Semaphore 13 register

Offset: 0x34, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R14

Semaphore 14 register

Offset: 0x38, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R15

Semaphore 15 register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R16

Semaphore 16 register

Offset: 0x40, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R17

Semaphore 17 register

Offset: 0x44, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R18

Semaphore 18 register

Offset: 0x48, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R19

Semaphore 19 register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R20

Semaphore 20 register

Offset: 0x50, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R21

Semaphore 21 register

Offset: 0x54, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R22

Semaphore 22 register

Offset: 0x58, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R23

Semaphore 23 register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R24

Semaphore 24 register

Offset: 0x60, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R25

Semaphore 25 register

Offset: 0x64, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R26

Semaphore 26 register

Offset: 0x68, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R27

Semaphore 27 register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R28

Semaphore 28 register

Offset: 0x70, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R29

Semaphore 29 register

Offset: 0x74, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R30

Semaphore 30 register

Offset: 0x78, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

R31

Semaphore 31 register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw				PROCID rw

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR0

Semaphore 0 read lock register

Offset: 0x80, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR1

Semaphore 1 read lock register

Offset: 0x84, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR2

Semaphore 2 read lock register

Offset: 0x88, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR3

Semaphore 3 read lock register

Offset: 0x8C, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR4

Semaphore 4 read lock read lock register

Offset: 0x90, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR5

Semaphore 5 read lock register

Offset: 0x94, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR6

Semaphore 6 read lock register

Offset: 0x98, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR7

Semaphore 7 read lock register

Offset: 0x9C, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR8

Semaphore 8 read lock register

Offset: 0xA0, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR9

Semaphore 9 read lock register

Offset: 0xA4, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR10

Semaphore 10 read lock register

Offset: 0xA8, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR11

Semaphore 11 read lock register

Offset: 0xAC, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR12

Semaphore 12 read lock register

Offset: 0xB0, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR13

Semaphore 13 read lock register

Offset: 0xB4, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR14

Semaphore 14 read lock register

Offset: 0xB8, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR15

Semaphore 15 read lock register

Offset: 0xBC, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR16

Semaphore 16 read lock register

Offset: 0xC0, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR17

Semaphore 17 read lock register

Offset: 0xC4, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR18

Semaphore 18 read lock register

Offset: 0xC8, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR19

Semaphore 19 read lock register

Offset: 0xCC, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR20

Semaphore 20 read lock register

Offset: 0xD0, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR21

Semaphore 21 read lock register

Offset: 0xD4, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR22

Semaphore 22 read lock register

Offset: 0xD8, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR23

Semaphore 23 read lock register

Offset: 0xDC, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR24

Semaphore 24 read lock register

Offset: 0xE0, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR25

Semaphore 25 read lock register

Offset: 0xE4, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR26

Semaphore 26 read lock register

Offset: 0xE8, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR27

Semaphore 27 read lock register

Offset: 0xEC, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR28

Semaphore 28 read lock register

Offset: 0xF0, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR29

Semaphore 29 read lock register

Offset: 0xF4, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR30

Semaphore 30 read lock register

Offset: 0xF8, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

RLR31

Semaphore 31 read lock register

Offset: 0xFC, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LOCK r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID r				PROCID r

Toggle Fields.

PROCID

Bits 0-7: Semaphore ProcessID.

COREID

Bits 8-11: Semaphore CoreID.

LOCK

Bit 31: lock indication.

C1IER0

HSEM Interrupt enable register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISEm rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISEm rw

Toggle Fields.

ISEm

Bits 0-31: CPU(n) semaphore m enable bit.

C1ICR

HSEM Interrupt clear register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISCm rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISCm rw

Toggle Fields.

ISCm

Bits 0-31: CPU(n) semaphore m clear bit.

C1ISR

HSEM Interrupt status register

Offset: 0x108, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISFm r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISFm r

Toggle Fields.

ISFm

Bits 0-31: CPU(n) semaphore m status bit before enable (mask).

C1MISR

HSEM Masked interrupt status register

Offset: 0x10C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MISFm r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISFm r

Toggle Fields.

MISFm

Bits 0-31: masked CPU(n) semaphore m status bit after enable (mask)..

C2IER0

HSEM Interrupt enable register

Offset: 0x110, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISEm rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISEm rw

Toggle Fields.

ISEm

Bits 0-31: CPU(2) semaphore m enable bit..

C2ICR

HSEM Interrupt clear register

Offset: 0x114, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISCm rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISCm rw

Toggle Fields.

ISCm

Bits 0-31: CPU(2) semaphore m clear bit.

C2ISR

HSEM Interrupt status register

Offset: 0x118, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ISFm r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ISFm r

Toggle Fields.

ISFm

Bits 0-31: CPU(2) semaphore m status bit before enable (mask)..

C2MISR

HSEM Masked interrupt status register

Offset: 0x11C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MISFm r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MISFm r

Toggle Fields.

MISFm

Bits 0-31: masked CPU(2) semaphore m status bit after enable (mask)..

CR

Semaphore Clear register

Offset: 0x140, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				COREID rw

Toggle Fields.

COREID

Bits 8-11: CoreID of semaphore to be cleared.

KEY

Bits 16-31: Semaphore clear Key.

KEYR

Interrupt clear register

Offset: 0x144, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
KEY rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

KEY

Bits 16-31: Semaphore Clear Key.

HWCFGR2

Semaphore hardware configuration register 2

Offset: 0x3EC, reset: 0x00000084, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MASTERID4 r				MASTERID3 r				MASTERID2 r				MASTERID1 r

Toggle Fields.

MASTERID1

Bits 0-3: Hardware Configuration valid bus masters ID1.

MASTERID2

Bits 4-7: Hardware Configuration valid bus masters ID2.

MASTERID3

Bits 8-11: Hardware Configuration valid bus masters ID3.

MASTERID4

Bits 12-15: Hardware Configuration valid bus masters ID4.

HWCFGR1

Semaphore hardware configuration register 1

Offset: 0x3F0, reset: 0x00000220, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBINT r				NBSEM r

Toggle Fields.

NBSEM

Bits 0-7: Hardware Configuration number of semaphores.

NBINT

Bits 8-11: Hardware Configuration number of interrupts supported number of master IDs.

VERR

HSEM version register

Offset: 0x3F4, reset: 0x00000020, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields.

MINREV

Bits 0-3: Minor Revision.

MAJREV

Bits 4-7: Major Revision.

IPIDR

HSEM indentification register

Offset: 0x3F8, reset: 0x00100072, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle Fields.

ID

Bits 0-31: Identification Code.

SIDR

HSEM size indentification register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields.

SID

Bits 0-31: Size Identification Code.

I2C1

0x40005400: Inter-integrated circuit

17/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle Fields.

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle Fields.

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle Fields.

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

I2C3

0x40005C00: Inter-integrated circuit

17/76 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PECEN rw	ALERTEN rw	SMBDEN rw	SMBHEN rw	GCEN rw	WUPEN rw	NOSTRETCH rw	SBC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDMAEN rw	TXDMAEN rw		ANFOFF rw	DNF rw				ERRIE rw	TCIE rw	STOPIE rw	NACKIE rw	ADDRIE rw	RXIE rw	TXIE rw	PE rw

Toggle Fields.

PE

Bit 0: Peripheral enable.

TXIE

Bit 1: TX Interrupt enable.

RXIE

Bit 2: RX Interrupt enable.

ADDRIE

Bit 3: Address match interrupt enable (slave only).

NACKIE

Bit 4: Not acknowledge received interrupt enable.

STOPIE

Bit 5: STOP detection Interrupt enable.

TCIE

Bit 6: Transfer Complete interrupt enable.

ERRIE

Bit 7: Error interrupts enable.

DNF

Bits 8-11: Digital noise filter.

ANFOFF

Bit 12: Analog noise filter OFF.

TXDMAEN

Bit 14: DMA transmission requests enable.

RXDMAEN

Bit 15: DMA reception requests enable.

SBC

Bit 16: Slave byte control.

NOSTRETCH

Bit 17: Clock stretching disable.

WUPEN

Bit 18: Wakeup from STOP enable.

GCEN

Bit 19: General call enable.

SMBHEN

Bit 20: SMBus Host address enable.

SMBDEN

Bit 21: SMBus Device Default address enable.

ALERTEN

Bit 22: SMBUS alert enable.

PECEN

Bit 23: PEC enable.

CR2

Control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					PECBYTE rw	AUTOEND rw	RELOAD rw	NBYTES rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NACK rw	STOP rw	START rw	HEAD10R rw	ADD10 rw	RD_WRN rw	SADD rw

Toggle Fields.

SADD

Bits 0-9: Slave address bit (master mode).

RD_WRN

Bit 10: Transfer direction (master mode).

ADD10

Bit 11: 10-bit addressing mode (master mode).

HEAD10R

Bit 12: 10-bit address header only read direction (master receiver mode).

START

Bit 13: Start generation.

STOP

Bit 14: Stop generation (master mode).

NACK

Bit 15: NACK generation (slave mode).

NBYTES

Bits 16-23: Number of bytes.

RELOAD

Bit 24: NBYTES reload mode.

AUTOEND

Bit 25: Automatic end mode (master mode).

PECBYTE

Bit 26: Packet error checking byte.

OAR1

Own address register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA1EN rw					OA1MODE rw	OA1 rw

Toggle Fields.

OA1

Bits 0-9: Interface address.

OA1MODE

Bit 10: Own Address 1 10-bit mode.

OA1EN

Bit 15: Own Address 1 enable.

OAR2

Own address register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OA2EN rw					OA2MSK rw			OA2 rw

Toggle Fields.

OA2

Bits 1-7: Interface address.

OA2MSK

Bits 8-10: Own Address 2 masks.

OA2EN

Bit 15: Own Address 2 enable.

TIMINGR

Timing register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESC rw								SCLDEL rw				SDADEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SCLH rw								SCLL rw

Toggle Fields.

SCLL

Bits 0-7: SCL low period (master mode).

SCLH

Bits 8-15: SCL high period (master mode).

SDADEL

Bits 16-19: Data hold time.

SCLDEL

Bits 20-23: Data setup time.

PRESC

Bits 28-31: Timing prescaler.

TIMEOUTR

Status register 1

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TEXTEN rw				TIMEOUTB rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMOUTEN rw			TIDLE rw	TIMEOUTA rw

Toggle Fields.

TIMEOUTA

Bits 0-11: Bus timeout A.

TIDLE

Bit 12: Idle clock timeout detection.

TIMOUTEN

Bit 15: Clock timeout enable.

TIMEOUTB

Bits 16-27: Bus timeout B.

TEXTEN

Bit 31: Extended clock timeout enable.

ISR

Interrupt and Status register

Offset: 0x18, reset: 0x00000001, access: Unspecified

15/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								ADDCODE r							DIR r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BUSY r		ALERT r	TIMEOUT r	PECERR r	OVR r	ARLO r	BERR r	TCR r	TC r	STOPF r	NACKF r	ADDR r	RXNE r	TXIS rw	TXE rw

Toggle Fields.

TXE

Bit 0: Transmit data register empty (transmitters).

TXIS

Bit 1: Transmit interrupt status (transmitters).

RXNE

Bit 2: Receive data register not empty (receivers).

ADDR

Bit 3: Address matched (slave mode).

NACKF

Bit 4: Not acknowledge received flag.

STOPF

Bit 5: Stop detection flag.

TC

Bit 6: Transfer Complete (master mode).

TCR

Bit 7: Transfer Complete Reload.

BERR

Bit 8: Bus error.

ARLO

Bit 9: Arbitration lost.

OVR

Bit 10: Overrun/Underrun (slave mode).

PECERR

Bit 11: PEC Error in reception.

TIMEOUT

Bit 12: Timeout or t_low detection flag.

ALERT

Bit 13: SMBus alert.

BUSY

Bit 15: Bus busy.

DIR

Bit 16: Transfer direction (Slave mode).

ADDCODE

Bits 17-23: Address match code (Slave mode).

ICR

Interrupt clear register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ALERTCF w	TIMOUTCF w	PECCF w	OVRCF w	ARLOCF w	BERRCF w			STOPCF w	NACKCF w	ADDRCF w

Toggle Fields.

ADDRCF

Bit 3: Address Matched flag clear.

NACKCF

Bit 4: Not Acknowledge flag clear.

STOPCF

Bit 5: Stop detection flag clear.

BERRCF

Bit 8: Bus error flag clear.

ARLOCF

Bit 9: Arbitration lost flag clear.

OVRCF

Bit 10: Overrun/Underrun flag clear.

PECCF

Bit 11: PEC Error flag clear.

TIMOUTCF

Bit 12: Timeout detection flag clear.

ALERTCF

Bit 13: Alert flag clear.

PECR

PEC register

Offset: 0x20, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								PEC r

Toggle Fields.

PEC

Bits 0-7: Packet error checking register.

RXDR

Receive data register

Offset: 0x24, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								RXDATA r

Toggle Fields.

RXDATA

Bits 0-7: 8-bit receive data.

TXDR

Transmit data register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TXDATA rw

Toggle Fields.

TXDATA

Bits 0-7: 8-bit transmit data.

IPCC

0x58000C00: IPCC

17/69 fields covered. Toggle Registers.

C1CR

Control register CPU1

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TXFIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RXOIE rw

Toggle Fields.

RXOIE

Bit 0: processor 1 Receive channel occupied interrupt enable.

TXFIE

Bit 16: processor 1 Transmit channel free interrupt enable.

C1MR

Mask register CPU1

Offset: 0x4, reset: 0xFFFFFFFF, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CH6FM rw	CH5FM rw	CH4FM rw	CH3FM rw	CH2FM rw	CH1FM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6OM rw	CH5OM rw	CH4OM rw	CH3OM rw	CH2OM rw	CH1OM rw

Toggle Fields.

CH1OM

Bit 0: processor 1 Receive channel 1 occupied interrupt enable.

CH2OM

Bit 1: processor 1 Receive channel 2 occupied interrupt enable.

CH3OM

Bit 2: processor 1 Receive channel 3 occupied interrupt enable.

CH4OM

Bit 3: processor 1 Receive channel 4 occupied interrupt enable.

CH5OM

Bit 4: processor 1 Receive channel 5 occupied interrupt enable.

CH6OM

Bit 5: processor 1 Receive channel 6 occupied interrupt enable.

CH1FM

Bit 16: processor 1 Transmit channel 1 free interrupt mask.

CH2FM

Bit 17: processor 1 Transmit channel 2 free interrupt mask.

CH3FM

Bit 18: processor 1 Transmit channel 3 free interrupt mask.

CH4FM

Bit 19: processor 1 Transmit channel 4 free interrupt mask.

CH5FM

Bit 20: processor 1 Transmit channel 5 free interrupt mask.

CH6FM

Bit 21: processor 1 Transmit channel 6 free interrupt mask.

C1SCR

Status Set or Clear register CPU1

Offset: 0x8, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CH6S w	CH5S w	CH4S w	CH3S w	CH2S w	CH1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6C w	CH5C w	CH4C w	CH3C w	CH2C w	CH1C w

Toggle Fields.

CH1C

Bit 0: processor 1 Receive channel 1 status clear.

CH2C

Bit 1: processor 1 Receive channel 2 status clear.

CH3C

Bit 2: processor 1 Receive channel 3 status clear.

CH4C

Bit 3: processor 1 Receive channel 4 status clear.

CH5C

Bit 4: processor 1 Receive channel 5 status clear.

CH6C

Bit 5: processor 1 Receive channel 6 status clear.

CH1S

Bit 16: processor 1 Transmit channel 1 status set.

CH2S

Bit 17: processor 1 Transmit channel 2 status set.

CH3S

Bit 18: processor 1 Transmit channel 3 status set.

CH4S

Bit 19: processor 1 Transmit channel 4 status set.

CH5S

Bit 20: processor 1 Transmit channel 5 status set.

CH6S

Bit 21: processor 1 Transmit channel 6 status set.

C1TO2SR

CPU1 to CPU2 status register

Offset: 0xC, reset: 0x00000000, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6F r	CH5F r	CH4F r	CH3F r	CH2F r	CH1F r

Toggle Fields.

CH1F

Bit 0: processor 1 transmit to process 2 Receive channel 1 status flag.

CH2F

Bit 1: processor 1 transmit to process 2 Receive channel 2 status flag.

CH3F

Bit 2: processor 1 transmit to process 2 Receive channel 3 status flag.

CH4F

Bit 3: processor 1 transmit to process 2 Receive channel 4 status flag.

CH5F

Bit 4: processor 1 transmit to process 2 Receive channel 5 status flag.

CH6F

Bit 5: processor 1 transmit to process 2 Receive channel 6 status flag.

C2CR

Control register CPU2

Offset: 0x10, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TXFIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RXOIE rw

Toggle Fields.

RXOIE

Bit 0: processor 2 Receive channel occupied interrupt enable.

TXFIE

Bit 16: processor 2 Transmit channel free interrupt enable.

C2MR

Mask register CPU2

Offset: 0x14, reset: 0xFFFFFFFF, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CH6FM rw	CH5FM rw	CH4FM rw	CH3FM rw	CH2FM rw	CH1FM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6OM rw	CH5OM rw	CH4OM rw	CH3OM rw	CH2OM rw	CH1OM rw

Toggle Fields.

CH1OM

Bit 0: processor 2 Receive channel 1 occupied interrupt enable.

CH2OM

Bit 1: processor 2 Receive channel 2 occupied interrupt enable.

CH3OM

Bit 2: processor 2 Receive channel 3 occupied interrupt enable.

CH4OM

Bit 3: processor 2 Receive channel 4 occupied interrupt enable.

CH5OM

Bit 4: processor 2 Receive channel 5 occupied interrupt enable.

CH6OM

Bit 5: processor 2 Receive channel 6 occupied interrupt enable.

CH1FM

Bit 16: processor 2 Transmit channel 1 free interrupt mask.

CH2FM

Bit 17: processor 2 Transmit channel 2 free interrupt mask.

CH3FM

Bit 18: processor 2 Transmit channel 3 free interrupt mask.

CH4FM

Bit 19: processor 2 Transmit channel 4 free interrupt mask.

CH5FM

Bit 20: processor 2 Transmit channel 5 free interrupt mask.

CH6FM

Bit 21: processor 2 Transmit channel 6 free interrupt mask.

C2SCR

Status Set or Clear register CPU2

Offset: 0x18, reset: 0x00000000, access: write-only

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CH6S w	CH5S w	CH4S w	CH3S w	CH2S w	CH1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6C w	CH5C w	CH4C w	CH3C w	CH2C w	CH1C w

Toggle Fields.

CH1C

Bit 0: processor 2 Receive channel 1 status clear.

CH2C

Bit 1: processor 2 Receive channel 2 status clear.

CH3C

Bit 2: processor 2 Receive channel 3 status clear.

CH4C

Bit 3: processor 2 Receive channel 4 status clear.

CH5C

Bit 4: processor 2 Receive channel 5 status clear.

CH6C

Bit 5: processor 2 Receive channel 6 status clear.

CH1S

Bit 16: processor 2 Transmit channel 1 status set.

CH2S

Bit 17: processor 2 Transmit channel 2 status set.

CH3S

Bit 18: processor 2 Transmit channel 3 status set.

CH4S

Bit 19: processor 2 Transmit channel 4 status set.

CH5S

Bit 20: processor 2 Transmit channel 5 status set.

CH6S

Bit 21: processor 2 Transmit channel 6 status set.

C2TOC1SR

CPU2 to CPU1 status register

Offset: 0x1C, reset: 0x00000000, access: read-only

6/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										CH6F r	CH5F r	CH4F r	CH3F r	CH2F r	CH1F r

Toggle Fields.

CH1F

Bit 0: processor 2 transmit to process 1 Receive channel 1 status flag.

CH2F

Bit 1: processor 2 transmit to process 1 Receive channel 2 status flag.

CH3F

Bit 2: processor 2 transmit to process 1 Receive channel 3 status flag.

CH4F

Bit 3: processor 2 transmit to process 1 Receive channel 4 status flag.

CH5F

Bit 4: processor 2 transmit to process 1 Receive channel 5 status flag.

CH6F

Bit 5: processor 2 transmit to process 1 Receive channel 6 status flag.

HWCFGR

IPCC Hardware configuration register

Offset: 0x3F0, reset: 0x00000006, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								CHANNELS r

Toggle Fields.

CHANNELS

Bits 0-7: Number of channels per CPU supported by the IP, range 1 to 16.

VERR

IPCC version register

Offset: 0x3F4, reset: 0x00000010, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields.

MINREV

Bits 0-3: Minor Revision.

MAJREV

Bits 4-7: Major Revision.

IPIDR

IPCC indentification register

Offset: 0x3F8, reset: 0x00100071, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPID r

Toggle Fields.

IPID

Bits 0-31: Identification Code.

SIDR

IPCC size indentification register

Offset: 0x3FC, reset: 0xA3C5DD01, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields.

SID

Bits 0-31: Size Identification Code.

IWDG

0x40003000: Independent watchdog

3/7 fields covered. Toggle Registers.

KR

Key register

Offset: 0x0, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
KEY w

Toggle Fields.

KEY

Bits 0-15: Key value (write only, read 0x0000).

PR

Prescaler register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PR rw

Toggle Fields.

PR

Bits 0-2: Prescaler divider.

RLR

Reload register

Offset: 0x8, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				RL rw

Toggle Fields.

RL

Bits 0-11: Watchdog counter reload value.

SR

Status register

Offset: 0xC, reset: 0x00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													WVU r	RVU r	PVU r

Toggle Fields.

PVU

Bit 0: Watchdog prescaler value update.

RVU

Bit 1: Watchdog counter reload value update.

WVU

Bit 2: Watchdog counter window value update.

WINR

Window register

Offset: 0x10, reset: 0x00000FFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				WIN rw

Toggle Fields.

WIN

Bits 0-11: Watchdog counter window value.

LCD

0x40002400: Liquid crystal display controller

5/280 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							BUFEN rw	MUX_SEG rw	BIAS rw		DUTY rw			VSEL rw	LCDEN rw

Toggle Fields.

LCDEN

Bit 0: LCD controller enable.

VSEL

Bit 1: Voltage source selection.

DUTY

Bits 2-4: Duty selection.

BIAS

Bits 5-6: Bias selector.

MUX_SEG

Bit 7: Mux segment enable.

BUFEN

Bit 8: Voltage output buffer enable.

FCR

frame control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						PS rw				DIV rw				BLINK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BLINKF rw			CC rw			DEAD rw			PON rw			UDDIE rw		SOFIE rw	HD rw

Toggle Fields.

HD

Bit 0: High drive enable.

SOFIE

Bit 1: Start of frame interrupt enable.

UDDIE

Bit 3: Update display done interrupt enable.

PON

Bits 4-6: Pulse ON duration.

DEAD

Bits 7-9: Dead time duration.

CC

Bits 10-12: Contrast control.

BLINKF

Bits 13-15: Blink frequency selection.

BLINK

Bits 16-17: Blink mode selection.

DIV

Bits 18-21: DIV clock divider.

PS

Bits 22-25: PS 16-bit prescaler.

SR

status register

Offset: 0x8, reset: 0x00000020, access: Unspecified

5/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										FCRSF r	RDY r	UDD r	UDR rw	SOF r	ENS r

Toggle Fields.

ENS

Bit 0: ENS.

SOF

Bit 1: Start of frame flag.

UDR

Bit 2: Update display request.

UDD

Bit 3: Update Display Done.

RDY

Bit 4: Ready flag.

FCRSF

Bit 5: LCD Frame Control Register Synchronization flag.

CLR

clear register

Offset: 0xC, reset: 0x00000000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												UDDC w		SOFC w

Toggle Fields.

SOFC

Bit 1: Start of frame flag clear.

UDDC

Bit 3: Update display done clear.

RAM_COM0

display memory

Offset: 0x14, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM1

display memory

Offset: 0x1C, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM2

display memory

Offset: 0x24, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM3

display memory

Offset: 0x2C, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM4

display memory

Offset: 0x34, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM5

display memory

Offset: 0x3C, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM6

display memory

Offset: 0x44, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

RAM_COM7

display memory

Offset: 0x4C, reset: 0x00000000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
S31 rw	S30 rw	S29 rw	S28 rw	S27 rw	S26 rw	S25 rw	S24 rw	S23 rw	S22 rw	S21 rw	S20 rw	S19 rw	S18 rw	S17 rw	S16 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
S15 rw	S14 rw	S13 rw	S12 rw	S11 rw	S10 rw	S09 rw	S08 rw	S07 rw	S06 rw	S05 rw	S04 rw	S03 rw	S02 rw	S01 rw	S00 rw

Toggle Fields.

S00

Bit 0: S00.

S01

Bit 1: S01.

S02

Bit 2: S02.

S03

Bit 3: S03.

S04

Bit 4: S04.

S05

Bit 5: S05.

S06

Bit 6: S06.

S07

Bit 7: S07.

S08

Bit 8: S08.

S09

Bit 9: S09.

S10

Bit 10: S10.

S11

Bit 11: S11.

S12

Bit 12: S12.

S13

Bit 13: S13.

S14

Bit 14: S14.

S15

Bit 15: S15.

S16

Bit 16: S16.

S17

Bit 17: S17.

S18

Bit 18: S18.

S19

Bit 19: S19.

S20

Bit 20: S20.

S21

Bit 21: S21.

S22

Bit 22: S22.

S23

Bit 23: S23.

S24

Bit 24: S24.

S25

Bit 25: S25.

S26

Bit 26: S26.

S27

Bit 27: S27.

S28

Bit 28: S28.

S29

Bit 29: S29.

S30

Bit 30: S30.

S31

Bit 31: S31.

LPTIM1

0x40007C00: Low power timer

8/44 fields covered. Toggle Registers.

ISR

Interrupt and Status Register

Offset: 0x0, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWN r	UP r	ARROK r	CMPOK r	EXTTRIG r	ARRM r	CMPM r

Toggle Fields.

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNCF w	UPCF w	ARROKCF w	CMPOKCF w	EXTTRIGCF w	ARRMCF w	CMPMCF w

Toggle Fields.

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNIE rw	UPIE rw	ARROKIE rw	CMPOKIE rw	EXTTRIGIE rw	ARRMIE rw	CMPMIE rw

Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle Fields.

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle Fields.

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMP rw

Toggle Fields.

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields.

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle Fields.

CNT

Bits 0-15: Counter value.

OR

Option Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OR2 rw	OR1 rw

Toggle Fields.

OR1

Bit 0: Option register bit 1.

OR2

Bit 1: Option register bit 2.

LPTIM2

0x40009400: Low power timer

8/44 fields covered. Toggle Registers.

ISR

Interrupt and Status Register

Offset: 0x0, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWN r	UP r	ARROK r	CMPOK r	EXTTRIG r	ARRM r	CMPM r

Toggle Fields.

CMPM

Bit 0: Compare match.

ARRM

Bit 1: Autoreload match.

EXTTRIG

Bit 2: External trigger edge event.

CMPOK

Bit 3: Compare register update OK.

ARROK

Bit 4: Autoreload register update OK.

UP

Bit 5: Counter direction change down to up.

DOWN

Bit 6: Counter direction change up to down.

ICR

Interrupt Clear Register

Offset: 0x4, reset: 0x00000000, access: write-only

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNCF w	UPCF w	ARROKCF w	CMPOKCF w	EXTTRIGCF w	ARRMCF w	CMPMCF w

Toggle Fields.

CMPMCF

Bit 0: compare match Clear Flag.

ARRMCF

Bit 1: Autoreload match Clear Flag.

EXTTRIGCF

Bit 2: External trigger valid edge Clear Flag.

CMPOKCF

Bit 3: Compare register update OK Clear Flag.

ARROKCF

Bit 4: Autoreload register update OK Clear Flag.

UPCF

Bit 5: Direction change to UP Clear Flag.

DOWNCF

Bit 6: Direction change to down Clear Flag.

IER

Interrupt Enable Register

Offset: 0x8, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									DOWNIE rw	UPIE rw	ARROKIE rw	CMPOKIE rw	EXTTRIGIE rw	ARRMIE rw	CMPMIE rw

Toggle Fields.

CMPMIE

Bit 0: Compare match Interrupt Enable.

ARRMIE

Bit 1: Autoreload match Interrupt Enable.

EXTTRIGIE

Bit 2: External trigger valid edge Interrupt Enable.

CMPOKIE

Bit 3: Compare register update OK Interrupt Enable.

ARROKIE

Bit 4: Autoreload register update OK Interrupt Enable.

UPIE

Bit 5: Direction change to UP Interrupt Enable.

DOWNIE

Bit 6: Direction change to down Interrupt Enable.

CFGR

Configuration Register

Offset: 0xC, reset: 0x00000000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ENC rw	COUNTMODE rw	PRELOAD rw	WAVPOL rw	WAVE rw	TIMOUT rw	TRIGEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TRIGSEL rw				PRESC rw				TRGFLT rw			CKFLT rw		CKPOL rw		CKSEL rw

Toggle Fields.

CKSEL

Bit 0: Clock selector.

CKPOL

Bits 1-2: Clock Polarity.

CKFLT

Bits 3-4: Configurable digital filter for external clock.

TRGFLT

Bits 6-7: Configurable digital filter for trigger.

PRESC

Bits 9-11: Clock prescaler.

TRIGSEL

Bits 13-15: Trigger selector.

TRIGEN

Bits 17-18: Trigger enable and polarity.

TIMOUT

Bit 19: Timeout enable.

WAVE

Bit 20: Waveform shape.

WAVPOL

Bit 21: Waveform shape polarity.

PRELOAD

Bit 22: Registers update mode.

COUNTMODE

Bit 23: counter mode enabled.

ENC

Bit 24: Encoder mode enable.

CR

Control Register

Offset: 0x10, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											RSTARE rw	COUNTRST rw	CNTSTRT rw	SNGSTRT rw	ENABLE rw

Toggle Fields.

ENABLE

Bit 0: LPTIM Enable.

SNGSTRT

Bit 1: LPTIM start in single mode.

CNTSTRT

Bit 2: Timer start in continuous mode.

COUNTRST

Bit 3: Counter reset.

RSTARE

Bit 4: Reset after read enable.

CMP

Compare Register

Offset: 0x14, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CMP rw

Toggle Fields.

CMP

Bits 0-15: Compare value.

ARR

Autoreload Register

Offset: 0x18, reset: 0x00000001, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields.

ARR

Bits 0-15: Auto reload value.

CNT

Counter Register

Offset: 0x1C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT r

Toggle Fields.

CNT

Bits 0-15: Counter value.

OR

Option Register

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														OR2 rw	OR1 rw

Toggle Fields.

OR1

Bit 0: Option register bit 1.

OR2

Bit 1: Option register bit 2.

LPUART1

0x40008000: Universal synchronous asynchronous receiver transmitter

29/134 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT4 rw	DEAT3 rw	DEAT2 rw	DEAT1 rw	DEAT0 rw	DEDT4 rw	DEDT3 rw	DEDT2 rw	DEDT1 rw	DEDT0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle Fields.

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw				RTOEN rw	ABRMOD1 rw	ABRMOD0 rw	ABREN rw	MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle Fields.

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle Fields.

BRR

Bits 0-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle Fields.

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler.

MPU

0xE000ED90: Memory protection unit

6/19 fields covered. Toggle Registers.

MPU_TYPER

MPU type register

Offset: 0x0, reset: 0X00000800, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								IREGION r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DREGION r															SEPARATE r

Toggle Fields.

SEPARATE

Bit 0: Separate flag.

DREGION

Bits 8-15: Number of MPU data regions.

IREGION

Bits 16-23: Number of MPU instruction regions.

MPU_CTRL

MPU control register

Offset: 0x4, reset: 0X00000000, access: read-only

3/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													PRIVDEFENA r	HFNMIENA r	ENABLE r

Toggle Fields.

ENABLE

Bit 0: Enables the MPU.

HFNMIENA

Bit 1: Enables the operation of MPU during hard fault.

PRIVDEFENA

Bit 2: Enable priviliged software access to default memory map.

MPU_RNR

MPU region number register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REGION rw

Toggle Fields.

REGION

Bits 0-7: MPU region.

MPU_RBAR

MPU region base address register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR rw											VALID rw	REGION rw

Toggle Fields.

REGION

Bits 0-3: MPU region field.

VALID

Bit 4: MPU region number valid.

ADDR

Bits 5-31: Region base address field.

MPU_RASR

MPU region attribute and size register

Offset: 0x10, reset: 0X00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
			XN rw		AP rw					TEX rw			S rw	C rw	B rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SRD rw										SIZE rw					ENABLE rw

Toggle Fields.

ENABLE

Bit 0: Region enable bit..

SIZE

Bits 1-5: Size of the MPU protection region.

SRD

Bits 8-15: Subregion disable bits.

B

Bit 16: memory attribute.

C

Bit 17: memory attribute.

S

Bit 18: Shareable memory attribute.

TEX

Bits 19-21: memory attribute.

AP

Bits 24-26: Access permission.

XN

Bit 28: Instruction access disable bit.

NVIC

0xE000E100: Nested Vectored Interrupt Controller

2/82 fields covered. Toggle Registers.

ISER0

Interrupt Set-Enable Register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle Fields.

SETENA

Bits 0-31: SETENA.

ISER1

Interrupt Set-Enable Register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETENA rw

Toggle Fields.

SETENA

Bits 0-31: SETENA.

ICER0

Interrupt Clear-Enable Register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ICER1

Interrupt Clear-Enable Register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRENA rw

Toggle Fields.

CLRENA

Bits 0-31: CLRENA.

ISPR0

Interrupt Set-Pending Register

Offset: 0x100, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ISPR1

Interrupt Set-Pending Register

Offset: 0x104, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SETPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SETPEND rw

Toggle Fields.

SETPEND

Bits 0-31: SETPEND.

ICPR0

Interrupt Clear-Pending Register

Offset: 0x180, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

ICPR1

Interrupt Clear-Pending Register

Offset: 0x184, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CLRPEND rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CLRPEND rw

Toggle Fields.

CLRPEND

Bits 0-31: CLRPEND.

IABR0

Interrupt Active Bit Register

Offset: 0x200, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IABR1

Interrupt Active Bit Register

Offset: 0x204, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ACTIVE r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ACTIVE r

Toggle Fields.

ACTIVE

Bits 0-31: ACTIVE.

IPR0

Interrupt Priority Register

Offset: 0x300, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR1

Interrupt Priority Register

Offset: 0x304, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR2

Interrupt Priority Register

Offset: 0x308, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR3

Interrupt Priority Register

Offset: 0x30C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR4

Interrupt Priority Register

Offset: 0x310, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR5

Interrupt Priority Register

Offset: 0x314, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR6

Interrupt Priority Register

Offset: 0x318, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR7

Interrupt Priority Register

Offset: 0x31C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR8

Interrupt Priority Register

Offset: 0x320, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR9

Interrupt Priority Register

Offset: 0x324, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR10

Interrupt Priority Register

Offset: 0x328, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR11

Interrupt Priority Register

Offset: 0x32C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR12

Interrupt Priority Register

Offset: 0x330, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR13

Interrupt Priority Register

Offset: 0x334, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR14

Interrupt Priority Register

Offset: 0x338, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR15

Interrupt Priority Register

Offset: 0x33C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR16

Interrupt Priority Register

Offset: 0x340, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

IPR17

Interrupt Priority Register

Offset: 0x344, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IPR_N3 rw								IPR_N2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IPR_N1 rw								IPR_N0 rw

Toggle Fields.

IPR_N0

Bits 0-7: IPR_N0.

IPR_N1

Bits 8-15: IPR_N1.

IPR_N2

Bits 16-23: IPR_N2.

IPR_N3

Bits 24-31: IPR_N3.

NVIC_STIR

0xE000EF00: Nested vectored interrupt controller

0/1 fields covered. Toggle Registers.

STIR

Software trigger interrupt register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							INTID rw

Toggle Fields.

INTID

Bits 0-8: Software generated interrupt ID.

PKA

0x58002000: PKA

8/18 fields covered. Toggle Registers.

CR

Control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADDRERRIE rw	RAMERRIE rw		PROCENDIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		MODE rw											SECLVL rw	START rw	EN rw

Toggle Fields.

EN

Bit 0: Peripheral Enable.

START

Bit 1: Start the operation.

SECLVL

Bit 2: Security Enable.

MODE

Bits 8-13: PKA Operation Mode.

PROCENDIE

Bit 17: End of operation interrupt enable.

RAMERRIE

Bit 19: RAM error interrupt enable.

ADDRERRIE

Bit 20: Address error interrupt enable.

SR

PKA status register

Offset: 0x4, reset: 0x00000000, access: read-only

4/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADDRERRF r	RAMERRF r		PROCENDF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

BUSY

Bit 16: PKA Operation in progress.

PROCENDF

Bit 17: PKA End of Operation flag.

RAMERRF

Bit 19: RAM error flag.

ADDRERRF

Bit 20: Address error flag.

CLRFR

PKA clear flag register

Offset: 0x8, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											ADDRERRFC rw	RAMERRFC rw		PROCENDFC rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

PROCENDFC

Bit 17: Clear PKA End of Operation flag.

RAMERRFC

Bit 19: Clear RAM error flag.

ADDRERRFC

Bit 20: Clear Address error flag.

VERR

PKA version register

Offset: 0x1FF4, reset: 0x00000010, access: read-only

2/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								MAJREV r				MINREV r

Toggle Fields.

MINREV

Bits 0-3: Minor revision.

MAJREV

Bits 4-7: Major revision.

IPIDR

PKA identification register

Offset: 0x1FF8, reset: 0x00170061, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID r

Toggle Fields.

ID

Bits 0-31: Identification Code.

SIDR

PKA size ID register

Offset: 0x1FFC, reset: 0xA3C5DD08, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SID r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SID r

Toggle Fields.

SID

Bits 0-31: Side Identification Code.

PWR

0x58000400: Power control

29/237 fields covered. Toggle Registers.

CR1

Power control register 1

Offset: 0x0, reset: 0x00000200, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LPR rw				VOS rw		DBP rw			FPDS rw	FPDR rw		LPMS rw

Toggle Fields.

LPMS

Bits 0-2: Low-power mode selection for CPU1.

FPDR

Bit 4: Flash power down mode during LPRun for CPU1.

FPDS

Bit 5: Flash power down mode during LPsSleep for CPU1.

DBP

Bit 8: Disable backup domain write protection.

VOS

Bits 9-10: Voltage scaling range selection.

LPR

Bit 14: Low-power run.

CR2

Power control register 2

Offset: 0x4, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					USV rw				PVME3 rw		PVME1 rw	PLS rw			PVDE rw

Toggle Fields.

PVDE

Bit 0: Power voltage detector enable.

PLS

Bits 1-3: Power voltage detector level selection.

PVME1

Bit 4: Peripheral voltage monitoring 1 enable: VDDUSB vs. 1.2V.

PVME3

Bit 6: Peripheral voltage monitoring 3 enable: VDDA vs. 1.62V.

USV

Bit 10: VDDUSB USB supply valid.

CR3

Power control register 3

Offset: 0x8, reset: 0x00008000, access: read-write

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIWUL rw	EC2H rw	E802A rw	ECRPE rw	EBLEA rw	APC rw	RRS rw	EBORHSDFB rw				EWUP5 rw	EWUP4 rw	EWUP3 rw	EWUP2 rw	EWUP1 rw

Toggle Fields.

EWUP1

Bit 0: Enable Wakeup pin WKUP1.

EWUP2

Bit 1: Enable Wakeup pin WKUP2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3.

EWUP4

Bit 3: Enable Wakeup pin WKUP4.

EWUP5

Bit 4: Enable Wakeup pin WKUP5.

EBORHSDFB

Bit 8: Enable BORH and Step Down counverter forced in Bypass interrups for CPU1.

RRS

Bit 9: SRAM2a retention in Standby mode.

APC

Bit 10: Apply pull-up and pull-down configuration.

EBLEA

Bit 11: Enable BLE end of activity interrupt for CPU1.

ECRPE

Bit 12: Enable critical radio phase end of activity interrupt for CPU1.

E802A

Bit 13: Enable end of activity interrupt for CPU1.

EC2H

Bit 14: Enable CPU2 Hold interrupt for CPU1.

EIWUL

Bit 15: Enable internal wakeup line for CPU1.

CR4

Power control register 4

Offset: 0xC, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C2BOOT rw						VBRS rw	VBE rw				WP5 rw	WP4 rw	WP3 rw	WP2 rw	WP1 rw

Toggle Fields.

WP1

Bit 0: Wakeup pin WKUP1 polarity.

WP2

Bit 1: Wakeup pin WKUP2 polarity.

WP3

Bit 2: Wakeup pin WKUP3 polarity.

WP4

Bit 3: Wakeup pin WKUP4 polarity.

WP5

Bit 4: Wakeup pin WKUP5 polarity.

VBE

Bit 8: VBAT battery charging enable.

VBRS

Bit 9: VBAT battery charging resistor selection.

C2BOOT

Bit 15: BOOT CPU2 after reset or wakeup from Stop or Standby modes.

SR1

Power status register 1

Offset: 0x10, reset: 0x00000000, access: read-only

14/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUFI r	C2HF r	AF802 r	BLEAF r	CRPEF r	_802WUF r	BLEWUF r	BORHF r	SDFBF r			CWUF5 r	CWUF4 r	CWUF3 r	CWUF2 r	CWUF1 r

Toggle Fields.

CWUF1

Bit 0: Wakeup flag 1.

CWUF2

Bit 1: Wakeup flag 2.

CWUF3

Bit 2: Wakeup flag 3.

CWUF4

Bit 3: Wakeup flag 4.

CWUF5

Bit 4: Wakeup flag 5.

SDFBF

Bit 7: Step Down converter forced in Bypass interrupt flag.

BORHF

Bit 8: BORH interrupt flag.

BLEWUF

Bit 9: BLE wakeup interrupt flag.

_802WUF

Bit 10: 802.15.4 wakeup interrupt flag.

CRPEF

Bit 11: Enable critical radio phase end of activity interrupt flag.

BLEAF

Bit 12: BLE end of activity interrupt flag.

AF802

Bit 13: 802.15.4 end of activity interrupt flag.

C2HF

Bit 14: CPU2 Hold interrupt flag.

WUFI

Bit 15: Internal Wakeup interrupt flag.

SR2

Power status register 2

Offset: 0x14, reset: 0x00000002, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PVMO3 r		PVMO1 r	PVDO r	VOSF r	REGLPF r	REGLPS r							SDSMPSF r	SDBF r

Toggle Fields.

SDBF

Bit 0: Step Down converter Bypass mode flag.

SDSMPSF

Bit 1: Step Down converter SMPS mode flag.

REGLPS

Bit 8: Low-power regulator started.

REGLPF

Bit 9: Low-power regulator flag.

VOSF

Bit 10: Voltage scaling flag.

PVDO

Bit 11: Power voltage detector output.

PVMO1

Bit 12: Peripheral voltage monitoring output: VDDUSB vs. 1.2 V.

PVMO3

Bit 14: Peripheral voltage monitoring output: VDDA vs. 1.62 V.

SCR

Power status clear register

Offset: 0x18, reset: 0x00000000, access: write-only

0/13 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	CC2HF w	C802AF w	CBLEAF w	CCRPEF w	C802WUF w	CBLEWUF w	CBORHF w	CSMPSFBF w			CWUF5 w	CWUF4 w	CWUF3 w	CWUF2 w	CWUF1 w

Toggle Fields.

CWUF1

Bit 0: Clear wakeup flag 1.

CWUF2

Bit 1: Clear wakeup flag 2.

CWUF3

Bit 2: Clear wakeup flag 3.

CWUF4

Bit 3: Clear wakeup flag 4.

CWUF5

Bit 4: Clear wakeup flag 5.

CSMPSFBF

Bit 7: Clear SMPS Step Down converter forced in Bypass interrupt flag.

CBORHF

Bit 8: Clear BORH interrupt flag.

CBLEWUF

Bit 9: Clear BLE wakeup interrupt flag.

C802WUF

Bit 10: Clear 802.15.4 wakeup interrupt flag.

CCRPEF

Bit 11: Clear critical radio phase end of activity interrupt flag.

CBLEAF

Bit 12: Clear BLE end of activity interrupt flag.

C802AF

Bit 13: Clear 802.15.4 end of activity interrupt flag.

CC2HF

Bit 14: Clear CPU2 Hold interrupt flag.

CR5

Power control register 5

Offset: 0x1C, reset: 0x00004270, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SDEB rw	SDBEN rw					SMPSCFG rw	BORHC rw		SDSC rw			SDVOS rw

Toggle Fields.

SDVOS

Bits 0-3: Step Down converter voltage output scaling.

SDSC

Bits 4-6: Step Down converter supplt startup current selection.

BORHC

Bit 8: BORH configuration selection.

SMPSCFG

Bit 9: VOS configuration selection (non user).

SDBEN

Bit 14: Enable Step Down converter Bypass mode enabled.

SDEB

Bit 15: Enable Step Down converter SMPS mode enabled.

PUCRA

Power Port A pull-up control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw		PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields.

PU0

Bit 0: Port A pull-up bit y (y=0..15).

PU1

Bit 1: Port A pull-up bit y (y=0..15).

PU2

Bit 2: Port A pull-up bit y (y=0..15).

PU3

Bit 3: Port A pull-up bit y (y=0..15).

PU4

Bit 4: Port A pull-up bit y (y=0..15).

PU5

Bit 5: Port A pull-up bit y (y=0..15).

PU6

Bit 6: Port A pull-up bit y (y=0..15).

PU7

Bit 7: Port A pull-up bit y (y=0..15).

PU8

Bit 8: Port A pull-up bit y (y=0..15).

PU9

Bit 9: Port A pull-up bit y (y=0..15).

PU10

Bit 10: Port A pull-up bit y (y=0..15).

PU11

Bit 11: Port A pull-up bit y (y=0..15).

PU12

Bit 12: Port A pull-up bit y (y=0..15).

PU13

Bit 13: Port A pull-up bit y (y=0..15).

PU15

Bit 15: Port A pull-up bit y (y=0..15).

PDCRA

Power Port A pull-down control register

Offset: 0x24, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PD14 rw		PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields.

PD0

Bit 0: Port A pull-down bit y (y=0..15).

PD1

Bit 1: Port A pull-down bit y (y=0..15).

PD2

Bit 2: Port A pull-down bit y (y=0..15).

PD3

Bit 3: Port A pull-down bit y (y=0..15).

PD4

Bit 4: Port A pull-down bit y (y=0..15).

PD5

Bit 5: Port A pull-down bit y (y=0..15).

PD6

Bit 6: Port A pull-down bit y (y=0..15).

PD7

Bit 7: Port A pull-down bit y (y=0..15).

PD8

Bit 8: Port A pull-down bit y (y=0..15).

PD9

Bit 9: Port A pull-down bit y (y=0..15).

PD10

Bit 10: Port A pull-down bit y (y=0..15).

PD11

Bit 11: Port A pull-down bit y (y=0..15).

PD12

Bit 12: Port A pull-down bit y (y=0..15).

PD14

Bit 14: Port A pull-down bit y (y=0..15).

PUCRB

Power Port B pull-up control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields.

PU0

Bit 0: Port B pull-up bit y (y=0..15).

PU1

Bit 1: Port B pull-up bit y (y=0..15).

PU2

Bit 2: Port B pull-up bit y (y=0..15).

PU3

Bit 3: Port B pull-up bit y (y=0..15).

PU4

Bit 4: Port B pull-up bit y (y=0..15).

PU5

Bit 5: Port B pull-up bit y (y=0..15).

PU6

Bit 6: Port B pull-up bit y (y=0..15).

PU7

Bit 7: Port B pull-up bit y (y=0..15).

PU8

Bit 8: Port B pull-up bit y (y=0..15).

PU9

Bit 9: Port B pull-up bit y (y=0..15).

PU10

Bit 10: Port B pull-up bit y (y=0..15).

PU11

Bit 11: Port B pull-up bit y (y=0..15).

PU12

Bit 12: Port B pull-up bit y (y=0..15).

PU13

Bit 13: Port B pull-up bit y (y=0..15).

PU14

Bit 14: Port B pull-up bit y (y=0..15).

PU15

Bit 15: Port B pull-up bit y (y=0..15).

PDCRB

Power Port B pull-down control register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw		PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields.

PD0

Bit 0: Port B pull-down bit y (y=0..15).

PD1

Bit 1: Port B pull-down bit y (y=0..15).

PD2

Bit 2: Port B pull-down bit y (y=0..15).

PD3

Bit 3: Port B pull-down bit y (y=0..15).

PD5

Bit 5: Port B pull-down bit y (y=0..15).

PD6

Bit 6: Port B pull-down bit y (y=0..15).

PD7

Bit 7: Port B pull-down bit y (y=0..15).

PD8

Bit 8: Port B pull-down bit y (y=0..15).

PD9

Bit 9: Port B pull-down bit y (y=0..15).

PD10

Bit 10: Port B pull-down bit y (y=0..15).

PD11

Bit 11: Port B pull-down bit y (y=0..15).

PD12

Bit 12: Port B pull-down bit y (y=0..15).

PD13

Bit 13: Port B pull-down bit y (y=0..15).

PD14

Bit 14: Port B pull-down bit y (y=0..15).

PD15

Bit 15: Port B pull-down bit y (y=0..15).

PUCRC

Power Port C pull-up control register

Offset: 0x30, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields.

PU0

Bit 0: Port C pull-up bit y (y=0..15).

PU1

Bit 1: Port C pull-up bit y (y=0..15).

PU2

Bit 2: Port C pull-up bit y (y=0..15).

PU3

Bit 3: Port C pull-up bit y (y=0..15).

PU4

Bit 4: Port C pull-up bit y (y=0..15).

PU5

Bit 5: Port C pull-up bit y (y=0..15).

PU6

Bit 6: Port C pull-up bit y (y=0..15).

PU7

Bit 7: Port C pull-up bit y (y=0..15).

PU8

Bit 8: Port C pull-up bit y (y=0..15).

PU9

Bit 9: Port C pull-up bit y (y=0..15).

PU10

Bit 10: Port C pull-up bit y (y=0..15).

PU11

Bit 11: Port C pull-up bit y (y=0..15).

PU12

Bit 12: Port C pull-up bit y (y=0..15).

PU13

Bit 13: Port C pull-up bit y (y=0..15).

PU14

Bit 14: Port C pull-up bit y (y=0..15).

PU15

Bit 15: Port C pull-up bit y (y=0..15).

PDCRC

Power Port C pull-down control register

Offset: 0x34, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields.

PD0

Bit 0: Port C pull-down bit y (y=0..15).

PD1

Bit 1: Port C pull-down bit y (y=0..15).

PD2

Bit 2: Port C pull-down bit y (y=0..15).

PD3

Bit 3: Port C pull-down bit y (y=0..15).

PD4

Bit 4: Port C pull-down bit y (y=0..15).

PD5

Bit 5: Port C pull-down bit y (y=0..15).

PD6

Bit 6: Port C pull-down bit y (y=0..15).

PD7

Bit 7: Port C pull-down bit y (y=0..15).

PD8

Bit 8: Port C pull-down bit y (y=0..15).

PD9

Bit 9: Port C pull-down bit y (y=0..15).

PD10

Bit 10: Port C pull-down bit y (y=0..15).

PD11

Bit 11: Port C pull-down bit y (y=0..15).

PD12

Bit 12: Port C pull-down bit y (y=0..15).

PD13

Bit 13: Port C pull-down bit y (y=0..15).

PD14

Bit 14: Port C pull-down bit y (y=0..15).

PD15

Bit 15: Port C pull-down bit y (y=0..15).

PUCRD

Power Port D pull-up control register

Offset: 0x38, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PU15 rw	PU14 rw	PU13 rw	PU12 rw	PU11 rw	PU10 rw	PU9 rw	PU8 rw	PU7 rw	PU6 rw	PU5 rw	PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields.

PU0

Bit 0: Port D pull-up bit y (y=0..15).

PU1

Bit 1: Port D pull-up bit y (y=0..15).

PU2

Bit 2: Port D pull-up bit y (y=0..15).

PU3

Bit 3: Port D pull-up bit y (y=0..15).

PU4

Bit 4: Port D pull-up bit y (y=0..15).

PU5

Bit 5: Port D pull-up bit y (y=0..15).

PU6

Bit 6: Port D pull-up bit y (y=0..15).

PU7

Bit 7: Port D pull-up bit y (y=0..15).

PU8

Bit 8: Port D pull-up bit y (y=0..15).

PU9

Bit 9: Port D pull-up bit y (y=0..15).

PU10

Bit 10: Port D pull-up bit y (y=0..15).

PU11

Bit 11: Port D pull-up bit y (y=0..15).

PU12

Bit 12: Port D pull-up bit y (y=0..15).

PU13

Bit 13: Port D pull-up bit y (y=0..15).

PU14

Bit 14: Port D pull-up bit y (y=0..15).

PU15

Bit 15: Port D pull-up bit y (y=0..15).

PDCRD

Power Port D pull-down control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PD15 rw	PD14 rw	PD13 rw	PD12 rw	PD11 rw	PD10 rw	PD9 rw	PD8 rw	PD7 rw	PD6 rw	PD5 rw	PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields.

PD0

Bit 0: Port D pull-down bit y (y=0..15).

PD1

Bit 1: Port D pull-down bit y (y=0..15).

PD2

Bit 2: Port D pull-down bit y (y=0..15).

PD3

Bit 3: Port D pull-down bit y (y=0..15).

PD4

Bit 4: Port D pull-down bit y (y=0..15).

PD5

Bit 5: Port D pull-down bit y (y=0..15).

PD6

Bit 6: Port D pull-down bit y (y=0..15).

PD7

Bit 7: Port D pull-down bit y (y=0..15).

PD8

Bit 8: Port D pull-down bit y (y=0..15).

PD9

Bit 9: Port D pull-down bit y (y=0..15).

PD10

Bit 10: Port D pull-down bit y (y=0..15).

PD11

Bit 11: Port D pull-down bit y (y=0..15).

PD12

Bit 12: Port D pull-down bit y (y=0..15).

PD13

Bit 13: Port D pull-down bit y (y=0..15).

PD14

Bit 14: Port D pull-down bit y (y=0..15).

PD15

Bit 15: Port D pull-down bit y (y=0..15).

PUCRE

Power Port E pull-up control register

Offset: 0x40, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PU4 rw	PU3 rw	PU2 rw	PU1 rw	PU0 rw

Toggle Fields.

PU0

Bit 0: Port E pull-up bit y (y=0..15).

PU1

Bit 1: Port E pull-up bit y (y=0..15).

PU2

Bit 2: Port E pull-up bit y (y=0..15).

PU3

Bit 3: Port E pull-up bit y (y=0..15).

PU4

Bit 4: Port E pull-up bit y (y=0..15).

PDCRE

Power Port E pull-down control register

Offset: 0x44, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											PD4 rw	PD3 rw	PD2 rw	PD1 rw	PD0 rw

Toggle Fields.

PD0

Bit 0: Port E pull-down bit y (y=0..15).

PD1

Bit 1: Port E pull-down bit y (y=0..15).

PD2

Bit 2: Port E pull-down bit y (y=0..15).

PD3

Bit 3: Port E pull-down bit y (y=0..15).

PD4

Bit 4: Port E pull-down bit y (y=0..15).

PUCRH

Power Port H pull-up control register

Offset: 0x58, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PU3 rw		PU1 rw	PU0 rw

Toggle Fields.

PU0

Bit 0: Port H pull-up bit y (y=0..1).

PU1

Bit 1: Port H pull-up bit y (y=0..1).

PU3

Bit 3: Port H pull-up bit y (y=0..1).

PDCRH

Power Port H pull-down control register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PD3 rw		PD1 rw	PD0 rw

Toggle Fields.

PD0

Bit 0: Port H pull-down bit y (y=0..1).

PD1

Bit 1: Port H pull-down bit y (y=0..1).

PD3

Bit 3: Port H pull-down bit y (y=0..1).

C2CR1

CPU2 Power control register 1

Offset: 0x80, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
_802EWKUP rw	BLEEWKUP rw									FPDS rw	FPDR rw		LPMS rw

Toggle Fields.

LPMS

Bits 0-2: Low-power mode selection for CPU2.

FPDR

Bit 4: Flash power down mode during LPRun for CPU2.

FPDS

Bit 5: Flash power down mode during LPSleep for CPU2.

BLEEWKUP

Bit 14: BLE external wakeup signal.

_802EWKUP

Bit 15: 802.15.4 external wakeup signal.

C2CR3

CPU2 Power control register 3

Offset: 0x84, reset: 0X00008000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
EIWUL rw			APC rw		E802WUP rw	EBLEWUP rw					EWUP5 rw	EWUP4 rw	EWUP3 rw	EWUP2 rw	EWUP1 rw

Toggle Fields.

EWUP1

Bit 0: Enable Wakeup pin WKUP1 for CPU2.

EWUP2

Bit 1: Enable Wakeup pin WKUP2 for CPU2.

EWUP3

Bit 2: Enable Wakeup pin WKUP3 for CPU2.

EWUP4

Bit 3: Enable Wakeup pin WKUP4 for CPU2.

EWUP5

Bit 4: Enable Wakeup pin WKUP5 for CPU2.

EBLEWUP

Bit 9: Enable BLE host wakeup interrupt for CPU2.

E802WUP

Bit 10: Enable 802.15.4 host wakeup interrupt for CPU2.

APC

Bit 12: Apply pull-up and pull-down configuration for CPU2.

EIWUL

Bit 15: Enable internal wakeup line for CPU2.

EXTSCR

Power status clear register

Offset: 0x88, reset: 0x00000000, access: Unspecified

7/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
C2DS r	C1DS r	CRPF r		C2STOPF r	C2SBF r	C1STOPF r	C1SBF r						CCRPF w	C2CSSF w	C1CSSF w

Toggle Fields.

C1CSSF

Bit 0: Clear CPU1 Stop Standby flags.

C2CSSF

Bit 1: Clear CPU2 Stop Standby flags.

CCRPF

Bit 2: Clear Critical Radio system phase.

C1SBF

Bit 8: System Standby flag for CPU1.

C1STOPF

Bit 9: System Stop flag for CPU1.

C2SBF

Bit 10: System Standby flag for CPU2.

C2STOPF

Bit 11: System Stop flag for CPU2.

CRPF

Bit 13: Critical Radio system phase.

C1DS

Bit 14: CPU1 deepsleep mode.

C2DS

Bit 15: CPU2 deepsleep mode.

QUADSPI

0xA0001000: QuadSPI interface

7/47 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRESCALER rw								PMM rw	APMS rw		TOIE rw	SMIE rw	FTIE rw	TCIE rw	TEIE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				FTHRES rw							SSHIFT rw	TCEN rw	DMAEN rw	ABORT rw	EN rw

Toggle Fields.

EN

Bit 0: Enable.

ABORT

Bit 1: Abort request.

DMAEN

Bit 2: DMA enable.

TCEN

Bit 3: Timeout counter enable.

SSHIFT

Bit 4: Sample shift.

FTHRES

Bits 8-11: FIFO threshold level.

TEIE

Bit 16: Transfer error interrupt enable.

TCIE

Bit 17: Transfer complete interrupt enable.

FTIE

Bit 18: FIFO threshold interrupt enable.

SMIE

Bit 19: Status match interrupt enable.

TOIE

Bit 20: TimeOut interrupt enable.

APMS

Bit 22: Automatic poll mode stop.

PMM

Bit 23: Polling match mode.

PRESCALER

Bits 24-31: Clock prescaler.

DCR

device configuration register

Offset: 0x4, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											FSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
					CSHT rw										CKMODE rw

Toggle Fields.

CKMODE

Bit 0: Mode 0 / mode 3.

CSHT

Bits 8-10: Chip select high time.

FSIZE

Bits 16-20: FLASH memory size.

SR

status register

Offset: 0x8, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FLEVEL r							BUSY r	TOF r	SMF r	FTF r	TCF r	TEF r

Toggle Fields.

TEF

Bit 0: Transfer error flag.

TCF

Bit 1: Transfer complete flag.

FTF

Bit 2: FIFO threshold flag.

SMF

Bit 3: Status match flag.

TOF

Bit 4: Timeout flag.

BUSY

Bit 5: Busy.

FLEVEL

Bits 8-12: FIFO level.

FCR

flag clear register

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											CTOF rw	CSMF rw		CTCF rw	CTEF rw

Toggle Fields.

CTEF

Bit 0: Clear transfer error flag.

CTCF

Bit 1: Clear transfer complete flag.

CSMF

Bit 3: Clear status match flag.

CTOF

Bit 4: Clear timeout flag.

DLR

data length register

Offset: 0x10, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DL rw

Toggle Fields.

DL

Bits 0-31: Data length.

CCR

communication configuration register

Offset: 0x14, reset: 0x00000000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DDRM rw			SIOO rw	FMODE rw		DMODE rw			DCYC rw					ABSIZE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABMODE rw		ADSIZE rw		ADMODE rw		IMODE rw		INSTRUCTION rw

Toggle Fields.

INSTRUCTION

Bits 0-7: Instruction.

IMODE

Bits 8-9: Instruction mode.

ADMODE

Bits 10-11: Address mode.

ADSIZE

Bits 12-13: Address size.

ABMODE

Bits 14-15: Alternate bytes mode.

ABSIZE

Bits 16-17: Alternate bytes size.

DCYC

Bits 18-22: Number of dummy cycles.

DMODE

Bits 24-25: Data mode.

FMODE

Bits 26-27: Functional mode.

SIOO

Bit 28: Send instruction only once mode.

DDRM

Bit 31: Double data rate mode.

AR

address register

Offset: 0x18, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADDRESS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDRESS rw

Toggle Fields.

ADDRESS

Bits 0-31: Address.

ABR

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ALTERNATE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ALTERNATE rw

Toggle Fields.

ALTERNATE

Bits 0-31: ALTERNATE.

DR

data register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle Fields.

DATA

Bits 0-31: Data.

PSMKR

polling status mask register

Offset: 0x24, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MASK rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MASK rw

Toggle Fields.

MASK

Bits 0-31: Status mask.

PSMAR

polling status match register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MATCH rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MATCH rw

Toggle Fields.

MATCH

Bits 0-31: Status match.

PIR

polling interval register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
INTERVAL rw

Toggle Fields.

INTERVAL

Bits 0-15: Polling interval.

LPTR

low-power timeout register

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIMEOUT rw

Toggle Fields.

TIMEOUT

Bits 0-15: Timeout period.

RCC

0x58000000: Reset and clock control

43/324 fields covered. Toggle Registers.

CR

Clock control register

Offset: 0x0, reset: 0x00000061, access: Unspecified

6/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				PLLSAI1RDY r	PLLSAI1ON rw	PLLRDY r	PLLON rw				HSEPRE rw	CSSON w	HSEBYP rw	HSERDY r	HSEON rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			HSIKERDY r	HSIASFS rw	HSIRDY r	HSIKERON rw	HSION rw	MSIRANGE rw					MSIPLLEN rw	MSIRDY r	MSION rw

Toggle Fields.

MSION

Bit 0: MSI clock enable.

MSIRDY

Bit 1: MSI clock ready flag.

MSIPLLEN

Bit 2: MSI clock PLL enable.

MSIRANGE

Bits 4-7: MSI clock ranges.

HSION

Bit 8: HSI clock enabled.

HSIKERON

Bit 9: HSI always enable for peripheral kernels.

HSIRDY

Bit 10: HSI clock ready flag.

HSIASFS

Bit 11: HSI automatic start from Stop.

HSIKERDY

Bit 12: HSI kernel clock ready flag for peripherals requests.

HSEON

Bit 16: HSE clock enabled.

HSERDY

Bit 17: HSE clock ready flag.

HSEBYP

Bit 18: HSE crystal oscillator bypass.

CSSON

Bit 19: HSE Clock security system enable.

HSEPRE

Bit 20: HSE sysclk and PLL M divider prescaler.

PLLON

Bit 24: Main PLL enable.

PLLRDY

Bit 25: Main PLL clock ready flag.

PLLSAI1ON

Bit 26: SAI1 PLL enable.

PLLSAI1RDY

Bit 27: SAI1 PLL clock ready flag.

ICSCR

Internal clock sources calibration register

Offset: 0x4, reset: 0x40000000, access: Unspecified

2/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	HSITRIM rw							HSICAL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSITRIM rw								MSICAL r

Toggle Fields.

MSICAL

Bits 0-7: MSI clock calibration.

MSITRIM

Bits 8-15: MSI clock trimming.

HSICAL

Bits 16-23: HSI clock calibration.

HSITRIM

Bits 24-30: HSI clock trimming.

CFGR

Clock configuration register

Offset: 0x8, reset: 0x00070000, access: Unspecified

4/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	MCOPRE rw			MCOSEL rw									PPRE2F r	PPRE1F r	HPREF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
STOPWUCK rw		PPRE2 rw			PPRE1 rw			HPRE rw				SWS r		SW rw

Toggle Fields.

SW

Bits 0-1: System clock switch.

SWS

Bits 2-3: System clock switch status.

HPRE

Bits 4-7: AHB prescaler.

PPRE1

Bits 8-10: PB low-speed prescaler (APB1).

PPRE2

Bits 11-13: APB high-speed prescaler (APB2).

STOPWUCK

Bit 15: Wakeup from Stop and CSS backup clock selection.

HPREF

Bit 16: AHB prescaler flag.

PPRE1F

Bit 17: APB1 prescaler flag.

PPRE2F

Bit 18: APB2 prescaler flag.

MCOSEL

Bits 24-27: Microcontroller clock output.

MCOPRE

Bits 28-30: Microcontroller clock output prescaler.

PLLCFGR

PLLSYS configuration register

Offset: 0xC, reset: 0x22040100, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PLLR rw			PLLREN rw	PLLQ rw			PLLQEN rw			PLLP rw					PLLPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PLLN rw								PLLM rw					PLLSRC rw

Toggle Fields.

PLLSRC

Bits 0-1: Main PLL, PLLSAI1 and PLLSAI2 entry clock source.

PLLM

Bits 4-6: Division factor M for the main PLL and audio PLL (PLLSAI1 and PLLSAI2) input clock.

PLLN

Bits 8-14: Main PLLSYS multiplication factor N.

PLLPEN

Bit 16: Main PLLSYSP output enable.

PLLP

Bits 17-21: Main PLL division factor P for PPLSYSSAICLK.

PLLQEN

Bit 24: Main PLLSYSQ output enable.

PLLQ

Bits 25-27: Main PLLSYS division factor Q for PLLSYSUSBCLK.

PLLREN

Bit 28: Main PLLSYSR PLLCLK output enable.

PLLR

Bits 29-31: Main PLLSYS division factor R for SYSCLK (system clock).

PLLSAI1CFGR

PLLSAI1 configuration register

Offset: 0x10, reset: 0x22040100, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PLLR rw			PLLREN rw	PLLQ rw			PLLQEN rw			PLLP rw					PLLPEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PLLN rw

Toggle Fields.

PLLN

Bits 8-14: SAIPLL multiplication factor for VCO.

PLLPEN

Bit 16: SAIPLL PLLSAI1CLK output enable.

PLLP

Bits 17-21: SAI1PLL division factor P for PLLSAICLK (SAI1clock).

PLLQEN

Bit 24: SAIPLL PLLSAIUSBCLK output enable.

PLLQ

Bits 25-27: SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock).

PLLREN

Bit 28: PLLSAI PLLADC1CLK output enable.

PLLR

Bits 29-31: PLLSAI division factor R for PLLADC1CLK (ADC clock).

CIER

Clock interrupt enable register

Offset: 0x18, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LSI2RDYIE rw	HSI48RDYIE rw	LSECSSIE rw			PLLSAI1RDYIE rw	PLLRDYIE rw	HSERDYIE rw	HSIRDYIE rw	MSIRDYIE rw	LSERDYIE rw	LSI1RDYIE rw

Toggle Fields.

LSI1RDYIE

Bit 0: LSI1 ready interrupt enable.

LSERDYIE

Bit 1: LSE ready interrupt enable.

MSIRDYIE

Bit 2: MSI ready interrupt enable.

HSIRDYIE

Bit 3: HSI ready interrupt enable.

HSERDYIE

Bit 4: HSE ready interrupt enable.

PLLRDYIE

Bit 5: PLLSYS ready interrupt enable.

PLLSAI1RDYIE

Bit 6: PLLSAI1 ready interrupt enable.

LSECSSIE

Bit 9: LSE clock security system interrupt enable.

HSI48RDYIE

Bit 10: HSI48 ready interrupt enable.

LSI2RDYIE

Bit 11: LSI2 ready interrupt enable.

CIFR

Clock interrupt flag register

Offset: 0x1C, reset: 0x00000000, access: read-only

11/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LSI2RDYF r	HSI48RDYF r	LSECSSF r	HSECSSF r		PLLSAI1RDYF r	PLLRDYF r	HSERDYF r	HSIRDYF r	MSIRDYF r	LSERDYF r	LSI1RDYF r

Toggle Fields.

LSI1RDYF

Bit 0: LSI1 ready interrupt flag.

LSERDYF

Bit 1: LSE ready interrupt flag.

MSIRDYF

Bit 2: MSI ready interrupt flag.

HSIRDYF

Bit 3: HSI ready interrupt flag.

HSERDYF

Bit 4: HSE ready interrupt flag.

PLLRDYF

Bit 5: PLL ready interrupt flag.

PLLSAI1RDYF

Bit 6: PLLSAI1 ready interrupt flag.

HSECSSF

Bit 8: HSE Clock security system interrupt flag.

LSECSSF

Bit 9: LSE Clock security system interrupt flag.

HSI48RDYF

Bit 10: HSI48 ready interrupt flag.

LSI2RDYF

Bit 11: LSI2 ready interrupt flag.

CICR

Clock interrupt clear register

Offset: 0x20, reset: 0x00000000, access: write-only

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				LSI2RDYC w	HSI48RDYC w	LSECSSC w	HSECSSC w		PLLSAI1RDYC w	PLLRDYC w	HSERDYC w	HSIRDYC w	MSIRDYC w	LSERDYC w	LSI1RDYC w

Toggle Fields.

LSI1RDYC

Bit 0: LSI1 ready interrupt clear.

LSERDYC

Bit 1: LSE ready interrupt clear.

MSIRDYC

Bit 2: MSI ready interrupt clear.

HSIRDYC

Bit 3: HSI ready interrupt clear.

HSERDYC

Bit 4: HSE ready interrupt clear.

PLLRDYC

Bit 5: PLL ready interrupt clear.

PLLSAI1RDYC

Bit 6: PLLSAI1 ready interrupt clear.

HSECSSC

Bit 8: HSE Clock security system interrupt clear.

LSECSSC

Bit 9: LSE Clock security system interrupt clear.

HSI48RDYC

Bit 10: HSI48 ready interrupt clear.

LSI2RDYC

Bit 11: LSI2 ready interrupt clear.

SMPSCR

Step Down converter control register

Offset: 0x24, reset: 0x00000301, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						SMPSSWS r				SMPSDIV rw				SMPSSEL rw

Toggle Fields.

SMPSSEL

Bits 0-1: Step Down converter clock selection.

SMPSDIV

Bits 4-5: Step Down converter clock prescaler.

SMPSSWS

Bits 8-9: Step Down converter clock switch status.

AHB1RSTR

AHB1 peripheral reset register

Offset: 0x28, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCRST rw										DMAMUXRST rw	DMA2RST rw	DMA1RST rw

Toggle Fields.

DMA1RST

Bit 0: DMA1 reset.

DMA2RST

Bit 1: DMA2 reset.

DMAMUXRST

Bit 2: DMAMUX reset.

CRCRST

Bit 12: CRC reset.

TSCRST

Bit 16: Touch Sensing Controller reset.

AHB2RSTR

AHB2 peripheral reset register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCRST rw						GPIOHRST rw			GPIOERST rw	GPIODRST rw	GPIOCRST rw	GPIOBRST rw	GPIOARST rw

Toggle Fields.

GPIOARST

Bit 0: IO port A reset.

GPIOBRST

Bit 1: IO port B reset.

GPIOCRST

Bit 2: IO port C reset.

GPIODRST

Bit 3: IO port D reset.

GPIOERST

Bit 4: IO port E reset.

GPIOHRST

Bit 7: IO port H reset.

ADCRST

Bit 13: ADC reset.

AES1RST

Bit 16: AES1 hardware accelerator reset.

AHB3RSTR

AHB3 peripheral reset register

Offset: 0x30, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHRST rw					IPCCRST rw	HSEMRST rw	RNGRST rw	AES2RST rw	PKARST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							QSPIRST rw

Toggle Fields.

QSPIRST

Bit 8: Quad SPI memory interface reset.

PKARST

Bit 16: PKA interface reset.

AES2RST

Bit 17: AES2 interface reset.

RNGRST

Bit 18: RNG interface reset.

HSEMRST

Bit 19: HSEM interface reset.

IPCCRST

Bit 20: IPCC interface reset.

FLASHRST

Bit 25: Flash interface reset.

APB1RSTR1

APB1 peripheral reset register 1

Offset: 0x38, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1RST rw					USBFSRST rw		CRSRST rw	I2C3RST rw		I2C1RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2RST rw					LCDRST rw									TIM2RST rw

Toggle Fields.

TIM2RST

Bit 0: TIM2 timer reset.

LCDRST

Bit 9: LCD interface reset.

SPI2RST

Bit 14: SPI2 reset.

I2C1RST

Bit 21: I2C1 reset.

I2C3RST

Bit 23: I2C3 reset.

CRSRST

Bit 24: CRS reset.

USBFSRST

Bit 26: USB FS reset.

LPTIM1RST

Bit 31: Low Power Timer 1 reset.

APB1RSTR2

APB1 peripheral reset register 2

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2RST rw					LPUART1RST rw

Toggle Fields.

LPUART1RST

Bit 0: Low-power UART 1 reset.

LPTIM2RST

Bit 5: Low-power timer 2 reset.

APB2RSTR

APB2 peripheral reset register

Offset: 0x40, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1RST rw			TIM17RST rw	TIM16RST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1RST rw		SPI1RST rw	TIM1RST rw

Toggle Fields.

TIM1RST

Bit 11: TIM1 timer reset.

SPI1RST

Bit 12: SPI1 reset.

USART1RST

Bit 14: USART1 reset.

TIM16RST

Bit 17: TIM16 timer reset.

TIM17RST

Bit 18: TIM17 timer reset.

SAI1RST

Bit 21: Serial audio interface 1 (SAI1) reset.

APB3RSTR

APB3 peripheral reset register

Offset: 0x44, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															RFRST rw

Toggle Fields.

RFRST

Bit 0: Radio system BLE reset.

AHB1ENR

AHB1 peripheral clock enable register

Offset: 0x48, reset: 0x00000100, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw										DMAMUXEN rw	DMA2EN rw	DMA1EN rw

Toggle Fields.

DMA1EN

Bit 0: DMA1 clock enable.

DMA2EN

Bit 1: DMA2 clock enable.

DMAMUXEN

Bit 2: DMAMUX clock enable.

CRCEN

Bit 12: CPU1 CRC clock enable.

TSCEN

Bit 16: Touch Sensing Controller clock enable.

AHB2ENR

AHB2 peripheral clock enable register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCEN rw						GPIOHEN rw			GPIOEEN rw	GPIODEN rw	GPIOCEN rw	GPIOBEN rw	GPIOAEN rw

Toggle Fields.

GPIOAEN

Bit 0: IO port A clock enable.

GPIOBEN

Bit 1: IO port B clock enable.

GPIOCEN

Bit 2: IO port C clock enable.

GPIODEN

Bit 3: IO port D clock enable.

GPIOEEN

Bit 4: IO port E clock enable.

GPIOHEN

Bit 7: IO port H clock enable.

ADCEN

Bit 13: ADC clock enable.

AES1EN

Bit 16: AES1 accelerator clock enable.

AHB3ENR

AHB3 peripheral clock enable register

Offset: 0x50, reset: 0x02080000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHEN rw					IPCCEN rw	HSEMEN rw	RNGEN rw	AES2EN rw	PKAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							QSPIEN rw

Toggle Fields.

QSPIEN

Bit 8: QSPIEN.

PKAEN

Bit 16: PKAEN.

AES2EN

Bit 17: AES2EN.

RNGEN

Bit 18: RNGEN.

HSEMEN

Bit 19: HSEMEN.

IPCCEN

Bit 20: IPCCEN.

FLASHEN

Bit 25: FLASHEN.

APB1ENR1

Offset: 0x58, reset: 0x00000400, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1EN rw					USBEN rw		CRSEN rw	I2C3EN rw		I2C1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2EN rw			WWDGEN rw	RTCAPBEN rw	LCDEN rw									TIM2EN rw

Toggle Fields.

TIM2EN

Bit 0: CPU1 TIM2 timer clock enable.

LCDEN

Bit 9: CPU1 LCD clock enable.

RTCAPBEN

Bit 10: CPU1 RTC APB clock enable.

WWDGEN

Bit 11: CPU1 Window watchdog clock enable.

SPI2EN

Bit 14: CPU1 SPI2 clock enable.

I2C1EN

Bit 21: CPU1 I2C1 clock enable.

I2C3EN

Bit 23: CPU1 I2C3 clock enable.

CRSEN

Bit 24: CPU1 CRS clock enable.

USBEN

Bit 26: CPU1 USB clock enable.

LPTIM1EN

Bit 31: CPU1 Low power timer 1 clock enable.

APB1ENR2

APB1 peripheral clock enable register 2

Offset: 0x5C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2EN rw					LPUART1EN rw

Toggle Fields.

LPUART1EN

Bit 0: CPU1 Low power UART 1 clock enable.

LPTIM2EN

Bit 5: CPU1 LPTIM2EN.

APB2ENR

Offset: 0x60, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1EN rw			TIM17EN rw	TIM16EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1EN rw		SPI1EN rw	TIM1EN rw

Toggle Fields.

TIM1EN

Bit 11: CPU1 TIM1 timer clock enable.

SPI1EN

Bit 12: CPU1 SPI1 clock enable.

USART1EN

Bit 14: CPU1 USART1clock enable.

TIM16EN

Bit 17: CPU1 TIM16 timer clock enable.

TIM17EN

Bit 18: CPU1 TIM17 timer clock enable.

SAI1EN

Bit 21: CPU1 SAI1 clock enable.

AHB1SMENR

AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x68, reset: 0x00011207, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCSMEN rw			SRAM1SMEN rw							DMAMUXSMEN rw	DMA2SMEN rw	DMA1SMEN rw

Toggle Fields.

DMA1SMEN

Bit 0: CPU1 DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: CPU1 DMA2 clocks enable during Sleep and Stop modes.

DMAMUXSMEN

Bit 2: CPU1 DMAMUX clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: CPU1 SRAM1 interface clocks enable during Sleep and Stop modes.

CRCSMEN

Bit 12: CPU1 CRCSMEN.

TSCSMEN

Bit 16: CPU1 Touch Sensing Controller clocks enable during Sleep and Stop modes.

AHB2SMENR

AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x6C, reset: 0x0001209F, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCFSSMEN rw						GPIOHSMEN rw			GPIOESMEN rw	GPIODSMEN rw	GPIOCSMEN rw	GPIOBSMEN rw	GPIOASMEN rw

Toggle Fields.

GPIOASMEN

Bit 0: CPU1 IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: CPU1 IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: CPU1 IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: CPU1 IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: CPU1 IO port E clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: CPU1 IO port H clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: CPU1 ADC clocks enable during Sleep and Stop modes.

AES1SMEN

Bit 16: CPU1 AES1 accelerator clocks enable during Sleep and Stop modes.

AHB3SMENR

AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x70, reset: 0x03070100, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHSMEN rw	SRAM2SMEN rw						RNGSMEN rw	AES2SMEN rw	PKASMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							QSPISMEN rw

Toggle Fields.

QSPISMEN

Bit 8: QSPISMEN.

PKASMEN

Bit 16: PKA accelerator clocks enable during CPU1 sleep mode.

AES2SMEN

Bit 17: AES2 accelerator clocks enable during CPU1 sleep mode.

RNGSMEN

Bit 18: True RNG clocks enable during CPU1 sleep mode.

SRAM2SMEN

Bit 24: SRAM2a and SRAM2b memory interface clocks enable during CPU1 sleep mode.

FLASHSMEN

Bit 25: Flash interface clocks enable during CPU1 sleep mode.

APB1SMENR1

Offset: 0x78, reset: 0x85A04E01, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1SMEN rw					USBSMEN rw		CRSMEN rw	I2C3SMEN rw		I2C1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2SMEN rw			WWDGSMEN rw	RTCAPBSMEN rw	LCDSMEN rw									TIM2SMEN rw

Toggle Fields.

TIM2SMEN

Bit 0: TIM2 timer clocks enable during CPU1 Sleep mode.

LCDSMEN

Bit 9: LCD clocks enable during CPU1 Sleep mode.

RTCAPBSMEN

Bit 10: RTC APB clocks enable during CPU1 Sleep mode.

WWDGSMEN

Bit 11: Window watchdog clocks enable during CPU1 Sleep mode.

SPI2SMEN

Bit 14: SPI2 clocks enable during CPU1 Sleep mode.

I2C1SMEN

Bit 21: I2C1 clocks enable during CPU1 Sleep mode.

I2C3SMEN

Bit 23: I2C3 clocks enable during CPU1 Sleep mode.

CRSMEN

Bit 24: CRS clocks enable during CPU1 Sleep mode.

USBSMEN

Bit 26: USB FS clocks enable during CPU1 Sleep mode.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during CPU1 Sleep mode.

APB1SMENR2

APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x7C, reset: 0x000000021, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2SMEN rw					LPUART1SMEN rw

Toggle Fields.

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during CPU1 Sleep mode.

LPTIM2SMEN

Bit 5: Low power timer 2 clocks enable during CPU1 Sleep mode.

APB2SMENR

Offset: 0x80, reset: 0x00265800, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1SMEN rw			TIM17SMEN rw	TIM16SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1SMEN rw		SPI1SMEN rw	TIM1SMEN rw

Toggle Fields.

TIM1SMEN

Bit 11: TIM1 timer clocks enable during CPU1 Sleep mode.

SPI1SMEN

Bit 12: SPI1 clocks enable during CPU1 Sleep mode.

USART1SMEN

Bit 14: USART1clocks enable during CPU1 Sleep mode.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during CPU1 Sleep mode.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during CPU1 Sleep mode.

SAI1SMEN

Bit 21: SAI1 clocks enable during CPU1 Sleep mode.

CCIPR

Offset: 0x88, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNGSEL rw		ADCSEL rw		CLK48SEL rw				SAI1SEL rw		LPTIM2SEL rw		LPTIM1SEL rw		I2C3SEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		I2C1SEL rw		LPUART1SEL rw										USART1SEL rw

Toggle Fields.

USART1SEL

Bits 0-1: USART1 clock source selection.

LPUART1SEL

Bits 10-11: LPUART1 clock source selection.

I2C1SEL

Bits 12-13: I2C1 clock source selection.

I2C3SEL

Bits 16-17: I2C3 clock source selection.

LPTIM1SEL

Bits 18-19: Low power timer 1 clock source selection.

LPTIM2SEL

Bits 20-21: Low power timer 2 clock source selection.

SAI1SEL

Bits 22-23: SAI1 clock source selection.

CLK48SEL

Bits 26-27: 48 MHz clock source selection.

ADCSEL

Bits 28-29: ADCs clock source selection.

RNGSEL

Bits 30-31: RNG clock source selection.

BDCR

Offset: 0x90, reset: 0x00000000, access: Unspecified

2/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
					LSCOSEL rw		LSCOEN rw								BDRST rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTCEN rw						RTCSEL rw			LSECSSD_ r	LSECSSON rw	LSEDRV rw		LSEBYP rw	LSERDY r	LSEON rw

Toggle Fields.

LSEON

Bit 0: LSE oscillator enable.

LSERDY

Bit 1: LSE oscillator ready.

LSEBYP

Bit 2: LSE oscillator bypass.

LSEDRV

Bits 3-4: SE oscillator drive capability.

LSECSSON

Bit 5: LSECSSON.

LSECSSD_

Bit 6: CSS on LSE failure detection.

RTCSEL

Bits 8-9: RTC clock source selection.

RTCEN

Bit 15: RTC clock enable.

BDRST

Bit 16: Backup domain software reset.

LSCOEN

Bit 24: Low speed clock output enable.

LSCOSEL

Bits 25-26: Low speed clock output selection.

CSR

Offset: 0x94, reset: 0x0C000000, access: Unspecified

11/17 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPWRRSTF r	WWDGRSTF r	IWDGRSTF r	SFTRSTF r	BORRSTF r	PINRSTF r	OBLRSTF r		RMVF rw							RFRSTS r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RFWKPSEL rw				LSI2BW rw						LSI2TRIMOK r	LSI2TRIMEN rw	LSI2RDY r	LSI2ON rw	LSI1RDY r	LSI1ON rw

Toggle Fields.

LSI1ON

Bit 0: LSI1 oscillator enabled.

LSI1RDY

Bit 1: LSI1 oscillator ready.

LSI2ON

Bit 2: LSI2 oscillator enabled.

LSI2RDY

Bit 3: LSI2 oscillator ready.

LSI2TRIMEN

Bit 4: LSI2 oscillator trimming enable.

LSI2TRIMOK

Bit 5: LSI2 oscillator trim OK.

LSI2BW

Bits 8-11: LSI2 oscillator bias configuration.

RFWKPSEL

Bits 14-15: RF system wakeup clock source selection.

RFRSTS

Bit 16: Radio system BLE and 802.15.4 reset status.

RMVF

Bit 23: Remove reset flag.

OBLRSTF

Bit 25: Option byte loader reset flag.

PINRSTF

Bit 26: Pin reset flag.

BORRSTF

Bit 27: BOR flag.

SFTRSTF

Bit 28: Software reset flag.

IWDGRSTF

Bit 29: Independent window watchdog reset flag.

WWDGRSTF

Bit 30: Window watchdog reset flag.

LPWRRSTF

Bit 31: Low-power reset flag.

CRRCR

Clock recovery RC register

Offset: 0x98, reset: 0x00000000, access: Unspecified

2/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
HSI48CAL r														HSI48RDY r	HSI48ON rw

Toggle Fields.

HSI48ON

Bit 0: HSI48 oscillator enabled.

HSI48RDY

Bit 1: HSI48 clock ready.

HSI48CAL

Bits 7-15: HSI48 clock calibration.

HSECR

Clock HSE register

Offset: 0x9C, reset: 0x00000030, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		HSETUNE r							HSEGMC rw			HSES rw			UNLOCKED rw

Toggle Fields.

UNLOCKED

Bit 0: Register lock system.

HSES

Bit 3: HSE Sense amplifier threshold.

HSEGMC

Bits 4-6: HSE current control.

HSETUNE

Bits 8-13: HSE capacitor tuning.

EXTCFGR

Extended clock recovery register

Offset: 0x108, reset: 0x00030000, access: Unspecified

3/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											RFCSS r			C2HPREF r	SHDHPREF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								C2HPRE rw				SHDHPRE rw

Toggle Fields.

SHDHPRE

Bits 0-3: Shared AHB prescaler.

C2HPRE

Bits 4-7: CPU2 AHB prescaler.

SHDHPREF

Bit 16: Shared AHB prescaler flag.

C2HPREF

Bit 17: CPU2 AHB prescaler flag.

RFCSS

Bit 20: RF clock source selected.

C2AHB1ENR

CPU2 AHB1 peripheral clock enable register

Offset: 0x148, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCEN rw			SRAM1EN rw							DMAMUXEN rw	DMA2EN rw	DMA1EN rw

Toggle Fields.

DMA1EN

Bit 0: CPU2 DMA1 clock enable.

DMA2EN

Bit 1: CPU2 DMA2 clock enable.

DMAMUXEN

Bit 2: CPU2 DMAMUX clock enable.

SRAM1EN

Bit 9: CPU2 SRAM1 clock enable.

CRCEN

Bit 12: CPU2 CRC clock enable.

TSCEN

Bit 16: CPU2 Touch Sensing Controller clock enable.

C2AHB2ENR

CPU2 AHB2 peripheral clock enable register

Offset: 0x14C, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCEN rw						GPIOHEN rw			GPIOEEN rw	GPIODEN rw	GPIOCEN rw	GPIOBEN rw	GPIOAEN rw

Toggle Fields.

GPIOAEN

Bit 0: CPU2 IO port A clock enable.

GPIOBEN

Bit 1: CPU2 IO port B clock enable.

GPIOCEN

Bit 2: CPU2 IO port C clock enable.

GPIODEN

Bit 3: CPU2 IO port D clock enable.

GPIOEEN

Bit 4: CPU2 IO port E clock enable.

GPIOHEN

Bit 7: CPU2 IO port H clock enable.

ADCEN

Bit 13: CPU2 ADC clock enable.

AES1EN

Bit 16: CPU2 AES1 accelerator clock enable.

C2AHB3ENR

CPU2 AHB3 peripheral clock enable register

Offset: 0x150, reset: 0x02080000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHEN rw					IPCCEN rw	HSEMEN rw	RNGEN rw	AES2EN rw	PKAEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

PKAEN

Bit 16: CPU2 PKAEN.

AES2EN

Bit 17: CPU2 AES2EN.

RNGEN

Bit 18: CPU2 RNGEN.

HSEMEN

Bit 19: CPU2 HSEMEN.

IPCCEN

Bit 20: CPU2 IPCCEN.

FLASHEN

Bit 25: CPU2 FLASHEN.

C2APB1ENR1

CPU2 APB1ENR1

Offset: 0x158, reset: 0x00000400, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1EN rw					USBEN rw		CRSEN rw	I2C3EN rw		I2C1EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2EN rw				RTCAPBEN rw	LCDEN rw									TIM2EN rw

Toggle Fields.

TIM2EN

Bit 0: CPU2 TIM2 timer clock enable.

LCDEN

Bit 9: CPU2 LCD clock enable.

RTCAPBEN

Bit 10: CPU2 RTC APB clock enable.

SPI2EN

Bit 14: CPU2 SPI2 clock enable.

I2C1EN

Bit 21: CPU2 I2C1 clock enable.

I2C3EN

Bit 23: CPU2 I2C3 clock enable.

CRSEN

Bit 24: CPU2 CRS clock enable.

USBEN

Bit 26: CPU2 USB clock enable.

LPTIM1EN

Bit 31: CPU2 Low power timer 1 clock enable.

C2APB1ENR2

CPU2 APB1 peripheral clock enable register 2

Offset: 0x15C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2EN rw					LPUART1EN rw

Toggle Fields.

LPUART1EN

Bit 0: CPU2 Low power UART 1 clock enable.

LPTIM2EN

Bit 5: CPU2 LPTIM2EN.

C2APB2ENR

CPU2 APB2ENR

Offset: 0x160, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1EN rw			TIM17EN rw	TIM16EN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1EN rw		SPI1EN rw	TIM1EN rw

Toggle Fields.

TIM1EN

Bit 11: CPU2 TIM1 timer clock enable.

SPI1EN

Bit 12: CPU2 SPI1 clock enable.

USART1EN

Bit 14: CPU2 USART1clock enable.

TIM16EN

Bit 17: CPU2 TIM16 timer clock enable.

TIM17EN

Bit 18: CPU2 TIM17 timer clock enable.

SAI1EN

Bit 21: CPU2 SAI1 clock enable.

C2APB3ENR

CPU2 APB3ENR

Offset: 0x164, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														EN802 rw	BLEEN rw

Toggle Fields.

BLEEN

Bit 0: CPU2 BLE interface clock enable.

EN802

Bit 1: CPU2 802.15.4 interface clock enable.

C2AHB1SMENR

CPU2 AHB1 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x168, reset: 0x00011207, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															TSCSMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CRCSMEN rw			SRAM1SMEN rw							DMAMUXSMEN rw	DMA2SMEN rw	DMA1SMEN rw

Toggle Fields.

DMA1SMEN

Bit 0: CPU2 DMA1 clocks enable during Sleep and Stop modes.

DMA2SMEN

Bit 1: CPU2 DMA2 clocks enable during Sleep and Stop modes.

DMAMUXSMEN

Bit 2: CPU2 DMAMUX clocks enable during Sleep and Stop modes.

SRAM1SMEN

Bit 9: SRAM1 interface clock enable during CPU1 CSleep mode.

CRCSMEN

Bit 12: CPU2 CRCSMEN.

TSCSMEN

Bit 16: CPU2 Touch Sensing Controller clocks enable during Sleep and Stop modes.

C2AHB2SMENR

CPU2 AHB2 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x16C, reset: 0x0001209F, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															AES1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		ADCFSSMEN rw						GPIOHSMEN rw			GPIOESMEN rw	GPIODSMEN rw	GPIOCSMEN rw	GPIOBSMEN rw	GPIOASMEN rw

Toggle Fields.

GPIOASMEN

Bit 0: CPU2 IO port A clocks enable during Sleep and Stop modes.

GPIOBSMEN

Bit 1: CPU2 IO port B clocks enable during Sleep and Stop modes.

GPIOCSMEN

Bit 2: CPU2 IO port C clocks enable during Sleep and Stop modes.

GPIODSMEN

Bit 3: CPU2 IO port D clocks enable during Sleep and Stop modes.

GPIOESMEN

Bit 4: CPU2 IO port E clocks enable during Sleep and Stop modes.

GPIOHSMEN

Bit 7: CPU2 IO port H clocks enable during Sleep and Stop modes.

ADCFSSMEN

Bit 13: CPU2 ADC clocks enable during Sleep and Stop modes.

AES1SMEN

Bit 16: CPU2 AES1 accelerator clocks enable during Sleep and Stop modes.

C2AHB3SMENR

CPU2 AHB3 peripheral clocks enable in Sleep and Stop modes register

Offset: 0x170, reset: 0x03070000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						FLASHSMEN rw	SRAM2SMEN rw						RNGSMEN rw	AES2SMEN rw	PKASMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

PKASMEN

Bit 16: PKA accelerator clocks enable during CPU2 sleep modes.

AES2SMEN

Bit 17: AES2 accelerator clocks enable during CPU2 sleep modes.

RNGSMEN

Bit 18: True RNG clocks enable during CPU2 sleep modes.

SRAM2SMEN

Bit 24: SRAM2a and SRAM2b memory interface clocks enable during CPU2 sleep modes.

FLASHSMEN

Bit 25: Flash interface clocks enable during CPU2 sleep modes.

C2APB1SMENR1

CPU2 APB1SMENR1

Offset: 0x178, reset: 0x85A04601, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
LPTIM1SMEN rw					USBSMEN rw		CRSMEN rw	I2C3SMEN rw		I2C1SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SPI2SMEN rw				RTCAPBSMEN rw	LCDSMEN rw									TIM2SMEN rw

Toggle Fields.

TIM2SMEN

Bit 0: TIM2 timer clocks enable during CPU2 Sleep mode.

LCDSMEN

Bit 9: LCD clocks enable during CPU2 Sleep mode.

RTCAPBSMEN

Bit 10: RTC APB clocks enable during CPU2 Sleep mode.

SPI2SMEN

Bit 14: SPI2 clocks enable during CPU2 Sleep mode.

I2C1SMEN

Bit 21: I2C1 clocks enable during CPU2 Sleep mode.

I2C3SMEN

Bit 23: I2C3 clocks enable during CPU2 Sleep mode.

CRSMEN

Bit 24: CRS clocks enable during CPU2 Sleep mode.

USBSMEN

Bit 26: USB FS clocks enable during CPU2 Sleep mode.

LPTIM1SMEN

Bit 31: Low power timer 1 clocks enable during CPU2 Sleep mode.

C2APB1SMENR2

CPU2 APB1 peripheral clocks enable in Sleep and Stop modes register 2

Offset: 0x17C, reset: 0x000000021, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										LPTIM2SMEN rw					LPUART1SMEN rw

Toggle Fields.

LPUART1SMEN

Bit 0: Low power UART 1 clocks enable during CPU2 Sleep mode.

LPTIM2SMEN

Bit 5: Low power timer 2 clocks enable during CPU2 Sleep mode.

C2APB2SMENR

CPU2 APB2SMENR

Offset: 0x180, reset: 0x00265800, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										SAI1SMEN rw			TIM17SMEN rw	TIM16SMEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	USART1SMEN rw		SPI1SMEN rw	TIM1SMEN rw

Toggle Fields.

TIM1SMEN

Bit 11: TIM1 timer clocks enable during CPU2 Sleep mode.

SPI1SMEN

Bit 12: SPI1 clocks enable during CPU2 Sleep mode.

USART1SMEN

Bit 14: USART1clocks enable during CPU2 Sleep mode.

TIM16SMEN

Bit 17: TIM16 timer clocks enable during CPU2 Sleep mode.

TIM17SMEN

Bit 18: TIM17 timer clocks enable during CPU2 Sleep mode.

SAI1SMEN

Bit 21: SAI1 clocks enable during CPU2 Sleep mode.

C2APB3SMENR

CPU2 APB3SMENR

Offset: 0x184, reset: 0x0000003, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SMEN802 rw	BLESMEN rw

Toggle Fields.

BLESMEN

Bit 0: BLE interface clocks enable during CPU2 Sleep mode.

SMEN802

Bit 1: 802.15.4 interface clocks enable during CPU2 Sleep modes.

RNG

0x58001000: Random number generator

4/9 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									BYP rw			IE rw	RNGEN rw

Toggle Fields.

RNGEN

Bit 2: Random number generator enable.

IE

Bit 3: Interrupt enable.

BYP

Bit 6: Bypass mode enable.

SR

status register

Offset: 0x4, reset: 0x00000000, access: Unspecified

3/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									SEIS rw	CEIS rw			SECS r	CECS r	DRDY r

Toggle Fields.

DRDY

Bit 0: Data ready.

CECS

Bit 1: Clock error current status.

SECS

Bit 2: Seed error current status.

CEIS

Bit 5: Clock error interrupt status.

SEIS

Bit 6: Seed error interrupt status.

DR

data register

Offset: 0x8, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RNDATA r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RNDATA r

Toggle Fields.

RNDATA

Bits 0-31: Random data.

RTC

0x40002800: Real-time clock

20/152 fields covered. Toggle Registers.

TR

time register

Offset: 0x0, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT rw			MNU rw					ST rw			SU rw

Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

DR

date register

Offset: 0x4, reset: 0x00002101, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								YT rw				YU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU rw			MT rw	MU rw						DT rw		DU rw

Toggle Fields.

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

YU

Bits 16-19: Year units in BCD format.

YT

Bits 20-23: Year tens in BCD format.

CR

control register

Offset: 0x8, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							ITSE rw	COE rw	OSEL rw		POL rw	COSEL rw	BKP rw	SUB1H rw	ADD1H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TSIE rw	WUTIE rw	ALRBIE rw	ALRAIE rw	TSE rw	WUTE rw	ALRBE rw	ALRAE rw		FMT rw	BYPSHAD rw	REFCKON rw	TSEDGE rw	WCKSEL rw

Toggle Fields.

WCKSEL

Bits 0-2: Wakeup clock selection.

TSEDGE

Bit 3: Time-stamp event active edge.

REFCKON

Bit 4: Reference clock detection enable (50 or 60 Hz).

BYPSHAD

Bit 5: Bypass the shadow registers.

FMT

Bit 6: Hour format.

ALRAE

Bit 8: Alarm A enable.

ALRBE

Bit 9: Alarm B enable.

WUTE

Bit 10: Wakeup timer enable.

TSE

Bit 11: Time stamp enable.

ALRAIE

Bit 12: Alarm A interrupt enable.

ALRBIE

Bit 13: Alarm B interrupt enable.

WUTIE

Bit 14: Wakeup timer interrupt enable.

TSIE

Bit 15: Time-stamp interrupt enable.

ADD1H

Bit 16: Add 1 hour (summer time change).

SUB1H

Bit 17: Subtract 1 hour (winter time change).

BKP

Bit 18: Backup.

COSEL

Bit 19: Calibration output selection.

POL

Bit 20: Output polarity.

OSEL

Bits 21-22: Output selection.

COE

Bit 23: Calibration output enable.

ITSE

Bit 24: timestamp on internal event enable.

ISR

initialization and status register

Offset: 0xC, reset: 0x00000007, access: Unspecified

6/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														ITSF rw	RECALPF r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TAMP3F rw	TAMP2F rw	TAMP1F rw	TSOVF rw	TSF rw	WUTF rw	ALRBF rw	ALRAF rw	INIT rw	INITF r	RSF rw	INITS r	SHPF rw	WUTWF r	ALRBWF r	ALRAWF r

Toggle Fields.

ALRAWF

Bit 0: Alarm A write flag.

ALRBWF

Bit 1: Alarm B write flag.

WUTWF

Bit 2: Wakeup timer write flag.

SHPF

Bit 3: Shift operation pending.

INITS

Bit 4: Initialization status flag.

RSF

Bit 5: Registers synchronization flag.

INITF

Bit 6: Initialization flag.

INIT

Bit 7: Initialization mode.

ALRAF

Bit 8: Alarm A flag.

ALRBF

Bit 9: Alarm B flag.

WUTF

Bit 10: Wakeup timer flag.

TSF

Bit 11: Time-stamp flag.

TSOVF

Bit 12: Time-stamp overflow flag.

TAMP1F

Bit 13: Tamper detection flag.

TAMP2F

Bit 14: RTC_TAMP2 detection flag.

TAMP3F

Bit 15: RTC_TAMP3 detection flag.

RECALPF

Bit 16: Recalibration pending Flag.

ITSF

Bit 17: INTERNAL TIME-STAMP FLAG.

PRER

prescaler register

Offset: 0x10, reset: 0x007F00FF, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PREDIV_A rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	PREDIV_S rw

Toggle Fields.

PREDIV_S

Bits 0-14: Synchronous prescaler factor.

PREDIV_A

Bits 16-22: Asynchronous prescaler factor.

WUTR

wakeup timer register

Offset: 0x14, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WUT rw

Toggle Fields.

WUT

Bits 0-15: Wakeup auto-reload value bits.

ALRMAR

alarm A register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm A seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm A minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm A hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm A date mask.

ALRMBR

alarm B register

Offset: 0x20, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MSK4 rw	WDSEL rw	DT rw		DU rw				MSK3 rw	PM rw	HT rw		HU rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MSK2 rw	MNT rw			MNU rw				MSK1 rw	ST rw			SU rw

Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MSK1

Bit 7: Alarm B seconds mask.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

MSK2

Bit 15: Alarm B minutes mask.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

MSK3

Bit 23: Alarm B hours mask.

DU

Bits 24-27: Date units or day in BCD format.

DT

Bits 28-29: Date tens in BCD format.

WDSEL

Bit 30: Week day selection.

MSK4

Bit 31: Alarm B date mask.

WPR

write protection register

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle Fields.

KEY

Bits 0-7: Write protection key.

SSR

sub second register

Offset: 0x28, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle Fields.

SS

Bits 0-15: Sub second value.

SHIFTR

shift control register

Offset: 0x2C, reset: 0x00000000, access: write-only

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD1S w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SUBFS w

Toggle Fields.

SUBFS

Bits 0-14: Subtract a fraction of a second.

ADD1S

Bit 31: Add one second.

TSTR

time stamp time register

Offset: 0x30, reset: 0x00000000, access: read-only

7/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									PM r	HT r		HU r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	MNT r			MNU r					ST r			SU r

Toggle Fields.

SU

Bits 0-3: Second units in BCD format.

ST

Bits 4-6: Second tens in BCD format.

MNU

Bits 8-11: Minute units in BCD format.

MNT

Bits 12-14: Minute tens in BCD format.

HU

Bits 16-19: Hour units in BCD format.

HT

Bits 20-21: Hour tens in BCD format.

PM

Bit 22: AM/PM notation.

TSDR

time stamp date register

Offset: 0x34, reset: 0x00000000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
WDU r			MT r	MU r						DT r		DU r

Toggle Fields.

DU

Bits 0-3: Date units in BCD format.

DT

Bits 4-5: Date tens in BCD format.

MU

Bits 8-11: Month units in BCD format.

MT

Bit 12: Month tens in BCD format.

WDU

Bits 13-15: Week day units.

TSSSR

timestamp sub second register

Offset: 0x38, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SS r

Toggle Fields.

SS

Bits 0-15: Sub second value.

CALR

calibration register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CALP rw	CALW8 rw	CALW16 rw					CALM rw

Toggle Fields.

CALM

Bits 0-8: Calibration minus.

CALW16

Bit 13: Use a 16-second calibration cycle period.

CALW8

Bit 14: Use an 8-second calibration cycle period.

CALP

Bit 15: Increase frequency of RTC by 488.5 ppm.

TAMPCR

tamper configuration register

Offset: 0x40, reset: 0x00000000, access: read-write

0/21 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							TAMP3MF rw	TAMP3NOERASE rw	TAMP3IE rw	TAMP2MF rw	TAMP2NOERASE rw	TAMP2IE rw	TAMP1MF rw	TAMP1NOERASE rw	TAMP1IE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TAMPPUDIS rw	TAMPPRCH rw		TAMPFLT rw		TAMPFREQ rw			TAMPTS rw	TAMP3TRG rw	TAMP3E rw	TAMP2TRG rw	TAMP2E rw	TAMPIE rw	TAMP1TRG rw	TAMP1E rw

Toggle Fields.

TAMP1E

Bit 0: Tamper 1 detection enable.

TAMP1TRG

Bit 1: Active level for tamper 1.

TAMPIE

Bit 2: Tamper interrupt enable.

TAMP2E

Bit 3: Tamper 2 detection enable.

TAMP2TRG

Bit 4: Active level for tamper 2.

TAMP3E

Bit 5: Tamper 3 detection enable.

TAMP3TRG

Bit 6: Active level for tamper 3.

TAMPTS

Bit 7: Activate timestamp on tamper detection event.

TAMPFREQ

Bits 8-10: Tamper sampling frequency.

TAMPFLT

Bits 11-12: Tamper filter count.

TAMPPRCH

Bits 13-14: Tamper precharge duration.

TAMPPUDIS

Bit 15: TAMPER pull-up disable.

TAMP1IE

Bit 16: Tamper 1 interrupt enable.

TAMP1NOERASE

Bit 17: Tamper 1 no erase.

TAMP1MF

Bit 18: Tamper 1 mask flag.

TAMP2IE

Bit 19: Tamper 2 interrupt enable.

TAMP2NOERASE

Bit 20: Tamper 2 no erase.

TAMP2MF

Bit 21: Tamper 2 mask flag.

TAMP3IE

Bit 22: Tamper 3 interrupt enable.

TAMP3NOERASE

Bit 23: Tamper 3 no erase.

TAMP3MF

Bit 24: Tamper 3 mask flag.

ALRMASSR

alarm A sub second register

Offset: 0x44, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle Fields.

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

ALRMBSSR

alarm B sub second register

Offset: 0x48, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MASKSS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	SS rw

Toggle Fields.

SS

Bits 0-14: Sub seconds value.

MASKSS

Bits 24-27: Mask the most-significant bits starting at this bit.

OR

option register

Offset: 0x4C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														RTC_OUT_RMP rw	RTC_ALARM_TYPE rw

Toggle Fields.

RTC_ALARM_TYPE

Bit 0: RTC_ALARM on PC13 output type.

RTC_OUT_RMP

Bit 1: RTC_OUT remap.

BKP0R

backup register

Offset: 0x50, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP1R

backup register

Offset: 0x54, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP2R

backup register

Offset: 0x58, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP3R

backup register

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP4R

backup register

Offset: 0x60, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP5R

backup register

Offset: 0x64, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP6R

backup register

Offset: 0x68, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP7R

backup register

Offset: 0x6C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP8R

backup register

Offset: 0x70, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP9R

backup register

Offset: 0x74, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP10R

backup register

Offset: 0x78, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP11R

backup register

Offset: 0x7C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP12R

backup register

Offset: 0x80, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP13R

backup register

Offset: 0x84, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP14R

backup register

Offset: 0x88, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP15R

backup register

Offset: 0x8C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP16R

backup register

Offset: 0x90, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP17R

backup register

Offset: 0x94, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP18R

backup register

Offset: 0x98, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

BKP19R

backup register

Offset: 0x9C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BKP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BKP rw

Toggle Fields.

BKP

Bits 0-31: BKP.

SAI1

0x40015400: Serial audio interface

16/122 fields covered. Toggle Registers.

GCR

Global configuration register

Offset: 0x0, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										SYNCOUT rw				SYNCIN rw

Toggle Fields.

SYNCIN

Bits 0-1: Synchronization inputs.

SYNCOUT

Bits 4-5: Synchronization outputs.

ACR1

AConfiguration register 1

Offset: 0x4, reset: 0x00000040, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MCKEN rw	OSR rw	MCJDIV rw						NODIV rw		DMAEN rw	SAIBEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OutDri rw	MONO rw	SYNCEN rw		CKSTR rw	LSBFIRST rw	DS rw				PRTCFG rw		MODE rw

Toggle Fields.

MODE

Bits 0-1: Audio block mode.

PRTCFG

Bits 2-3: Protocol configuration.

DS

Bits 5-7: Data size.

LSBFIRST

Bit 8: Least significant bit first.

CKSTR

Bit 9: Clock strobing edge.

SYNCEN

Bits 10-11: Synchronization enable.

MONO

Bit 12: Mono mode.

OutDri

Bit 13: Output drive.

SAIBEN

Bit 16: Audio block B enable.

DMAEN

Bit 17: DMA enable.

NODIV

Bit 19: No divider.

MCJDIV

Bits 20-25: Master clock divider.

OSR

Bit 26: Oversampling ratio for master clock.

MCKEN

Bit 27: Master clock generation enable.

ACR2

AConfiguration register 2

Offset: 0x8, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP rw		CPL rw	MUTECN rw						MUTEVAL rw	MUTE rw	TRIS rw	FFLUS rw	FTH rw

Toggle Fields.

FTH

Bits 0-2: FIFO threshold.

FFLUS

Bit 3: FIFO flush.

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

MUTEVAL

Bit 6: Mute value.

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

COMP

Bits 14-15: Companding mode.

AFRCR

Offset: 0xC, reset: 0x00000007, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FSOFF rw	FSPOL rw	FSDEF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FSALL rw							FRL rw

Toggle Fields.

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

FSOFF

Bit 18: Frame synchronization offset.

ASLOTR

ASlot register

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SLOTEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBSLOT rw				SLOTSZ rw			FBOFF rw

Toggle Fields.

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

AIM

AInterrupt mask register2

Offset: 0x14, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET rw	AFSDETIE rw	CNRDYIE rw	FREQIE rw	WCKCFG rw	MUTEDET rw	OVRUDRIE rw

Toggle Fields.

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

MUTEDET

Bit 1: Mute detection interrupt enable.

WCKCFG

Bit 2: Wrong clock configuration interrupt enable.

FREQIE

Bit 3: FIFO request interrupt enable.

CNRDYIE

Bit 4: Codec not ready interrupt enable.

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

LFSDET

Bit 6: Late frame synchronization detection interrupt enable.

ASR

AStatus register

Offset: 0x18, reset: 0x00000008, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FLVL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET r	AFSDET r	CNRDY r	FREQ r	WCKCFG r	MUTEDET r	OVRUDR r

Toggle Fields.

OVRUDR

Bit 0: Overrun / underrun.

MUTEDET

Bit 1: Mute detection.

WCKCFG

Bit 2: Wrong clock configuration flag. This bit is read only.

FREQ

Bit 3: FIFO request.

CNRDY

Bit 4: Codec not ready.

AFSDET

Bit 5: Anticipated frame synchronization detection.

LFSDET

Bit 6: Late frame synchronization detection.

FLVL

Bits 16-18: FIFO level threshold.

ACLRFR

AClear flag register

Offset: 0x1C, reset: 0x00000000, access: write-only

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET w	CAFSDET w	CNRDY w		WCKCFG w	MUTEDET w	OVRUDR w

Toggle Fields.

OVRUDR

Bit 0: Clear overrun / underrun.

MUTEDET

Bit 1: Mute detection flag.

WCKCFG

Bit 2: Clear wrong clock configuration flag.

CNRDY

Bit 4: Clear codec not ready flag.

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

LFSDET

Bit 6: Clear late frame synchronization detection flag.

ADR

AData register

Offset: 0x20, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle Fields.

DATA

Bits 0-31: Data.

BCR1

BConfiguration register 1

Offset: 0x24, reset: 0x00000040, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				MCKEN rw	OSR rw	MCJDIV rw						NODIV rw		DMAEN rw	SAIBEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		OutDri rw	MONO rw	SYNCEN rw		CKSTR rw	LSBFIRST rw	DS rw				PRTCFG rw		MODE rw

Toggle Fields.

MODE

Bits 0-1: Audio block mode.

PRTCFG

Bits 2-3: Protocol configuration.

DS

Bits 5-7: Data size.

LSBFIRST

Bit 8: Least significant bit first.

CKSTR

Bit 9: Clock strobing edge.

SYNCEN

Bits 10-11: Synchronization enable.

MONO

Bit 12: Mono mode.

OutDri

Bit 13: Output drive.

SAIBEN

Bit 16: Audio block B enable.

DMAEN

Bit 17: DMA enable.

NODIV

Bit 19: No divider.

MCJDIV

Bits 20-25: Master clock divider.

OSR

Bit 26: Oversampling ratio for master clock.

MCKEN

Bit 27: Master clock generation enable.

BCR2

BConfiguration register 2

Offset: 0x28, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
COMP rw		CPL rw	MUTECN rw						MUTEVAL rw	MUTE rw	TRIS rw	FFLUS rw	FTH rw

Toggle Fields.

FTH

Bits 0-2: FIFO threshold.

FFLUS

Bit 3: FIFO flush.

TRIS

Bit 4: Tristate management on data line.

MUTE

Bit 5: Mute.

MUTEVAL

Bit 6: Mute value.

MUTECN

Bits 7-12: Mute counter.

CPL

Bit 13: Complement bit.

COMP

Bits 14-15: Companding mode.

BFRCR

Offset: 0x2C, reset: 0x00000007, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FSOFF rw	FSPOL rw	FSDEF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	FSALL rw							FRL rw

Toggle Fields.

FRL

Bits 0-7: Frame length.

FSALL

Bits 8-14: Frame synchronization active level length.

FSDEF

Bit 16: Frame synchronization definition.

FSPOL

Bit 17: Frame synchronization polarity.

FSOFF

Bit 18: Frame synchronization offset.

BSLOTR

BSlot register

Offset: 0x30, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
SLOTEN rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				NBSLOT rw				SLOTSZ rw			FBOFF rw

Toggle Fields.

FBOFF

Bits 0-4: First bit offset.

SLOTSZ

Bits 6-7: Slot size.

NBSLOT

Bits 8-11: Number of slots in an audio frame.

SLOTEN

Bits 16-31: Slot enable.

BIM

BInterrupt mask register2

Offset: 0x34, reset: 0x00000000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDETIE rw	AFSDETIE rw	CNRDYIE rw	FREQIE rw	WCKCFG rw	MUTEDET rw	OVRUDRIE rw

Toggle Fields.

OVRUDRIE

Bit 0: Overrun/underrun interrupt enable.

MUTEDET

Bit 1: Mute detection interrupt enable.

WCKCFG

Bit 2: Wrong clock configuration interrupt enable.

FREQIE

Bit 3: FIFO request interrupt enable.

CNRDYIE

Bit 4: Codec not ready interrupt enable.

AFSDETIE

Bit 5: Anticipated frame synchronization detection interrupt enable.

LFSDETIE

Bit 6: Late frame synchronization detection interrupt enable.

BSR

BStatus register

Offset: 0x38, reset: 0x00000008, access: read-only

8/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													FLVL r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET r	AFSDET r	CNRDY r	FREQ r	WCKCFG r	MUTEDET r	OVRUDR r

Toggle Fields.

OVRUDR

Bit 0: Overrun / underrun.

MUTEDET

Bit 1: Mute detection.

WCKCFG

Bit 2: Wrong clock configuration flag.

FREQ

Bit 3: FIFO request.

CNRDY

Bit 4: Codec not ready.

AFSDET

Bit 5: Anticipated frame synchronization detection.

LFSDET

Bit 6: Late frame synchronization detection.

FLVL

Bits 16-18: FIFO level threshold.

BCLRFR

BClear flag register

Offset: 0x3C, reset: 0x00000000, access: write-only

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									LFSDET w	CAFSDET w	CNRDY w		WCKCFG w	MUTEDET w	OVRUDR w

Toggle Fields.

OVRUDR

Bit 0: Clear overrun / underrun.

MUTEDET

Bit 1: Mute detection flag.

WCKCFG

Bit 2: Clear wrong clock configuration flag.

CNRDY

Bit 4: Clear codec not ready flag.

CAFSDET

Bit 5: Clear anticipated frame synchronization detection flag.

LFSDET

Bit 6: Clear late frame synchronization detection flag.

BDR

BData register

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DATA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DATA rw

Toggle Fields.

DATA

Bits 0-31: Data.

PDMCR

PDM control register

Offset: 0x44, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				CKEN4 rw	CKEN3 rw	CKEN2 rw	CKEN1 rw			MICNBR rw					PDMEN rw

Toggle Fields.

PDMEN

Bit 0: PDM enable.

MICNBR

Bits 4-5: Number of microphones.

CKEN1

Bit 8: Clock enable of bitstream clock number 1.

CKEN2

Bit 9: Clock enable of bitstream clock number 2.

CKEN3

Bit 10: Clock enable of bitstream clock number 3.

CKEN4

Bit 11: Clock enable of bitstream clock number 4.

PDMDLY

PDM delay register

Offset: 0x48, reset: 0x00000000, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
	DLYM4R rw				DLYM4L rw				DLYM3R rw				DLYM3L rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	DLYM2R rw				DLYM2L rw				DLYM1R rw				DLYM1L rw

Toggle Fields.

DLYM1L

Bits 0-2: Delay line for first microphone of pair 1.

DLYM1R

Bits 4-6: Delay line for second microphone of pair 1.

DLYM2L

Bits 8-10: Delay line for first microphone of pair 2.

DLYM2R

Bits 12-14: Delay line for second microphone of pair 2.

DLYM3L

Bits 16-18: Delay line for first microphone of pair 3.

DLYM3R

Bits 20-22: Delay line for second microphone of pair 3.

DLYM4L

Bits 24-26: Delay line for first microphone of pair 4.

DLYM4R

Bits 28-30: Delay line for second microphone of pair 4.

SCB

0xE000ED00: System control block

5/74 fields covered. Toggle Registers.

CPUID

CPUID base register

Offset: 0x0, reset: 0x410FC241, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
Implementer r								Variant r				Constant r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PartNo r												Revision r

Toggle Fields.

Revision

Bits 0-3: Revision number.

PartNo

Bits 4-15: Part number of the processor.

Constant

Bits 16-19: Reads as 0xF.

Variant

Bits 20-23: Variant number.

Implementer

Bits 24-31: Implementer code.

ICSR

Interrupt control and state register

Offset: 0x4, reset: 0x00000000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NMIPENDSET rw			PENDSVSET rw	PENDSVCLR rw	PENDSTSET rw	PENDSTCLR rw			ISRPENDING rw				VECTPENDING rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VECTPENDING rw				RETTOBASE rw			VECTACTIVE rw

Toggle Fields.

VECTACTIVE

Bits 0-8: Active vector.

RETTOBASE

Bit 11: Return to base level.

VECTPENDING

Bits 12-18: Pending vector.

ISRPENDING

Bit 22: Interrupt pending flag.

PENDSTCLR

Bit 25: SysTick exception clear-pending bit.

PENDSTSET

Bit 26: SysTick exception set-pending bit.

PENDSVCLR

Bit 27: PendSV clear-pending bit.

PENDSVSET

Bit 28: PendSV set-pending bit.

NMIPENDSET

Bit 31: NMI set-pending bit..

VTOR

Vector table offset register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
		TBLOFF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TBLOFF rw

Toggle Fields.

TBLOFF

Bits 9-29: Vector table base offset field.

AIRCR

Application interrupt and reset control register

Offset: 0xC, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
VECTKEYSTAT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ENDIANESS rw					PRIGROUP rw								SYSRESETREQ rw	VECTCLRACTIVE rw	VECTRESET rw

Toggle Fields.

VECTRESET

Bit 0: VECTRESET.

VECTCLRACTIVE

Bit 1: VECTCLRACTIVE.

SYSRESETREQ

Bit 2: SYSRESETREQ.

PRIGROUP

Bits 8-10: PRIGROUP.

ENDIANESS

Bit 15: ENDIANESS.

VECTKEYSTAT

Bits 16-31: Register key.

SCR

System control register

Offset: 0x10, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											SEVEONPEND rw		SLEEPDEEP rw	SLEEPONEXIT rw

Toggle Fields.

SLEEPONEXIT

Bit 1: SLEEPONEXIT.

SLEEPDEEP

Bit 2: SLEEPDEEP.

SEVEONPEND

Bit 4: Send Event on Pending bit.

CCR

Configuration and control register

Offset: 0x14, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						STKALIGN rw	BFHFNMIGN rw				DIV_0_TRP rw	UNALIGN__TRP rw		USERSETMPEND rw	NONBASETHRDENA rw

Toggle Fields.

NONBASETHRDENA

Bit 0: Configures how the processor enters Thread mode.

USERSETMPEND

Bit 1: USERSETMPEND.

UNALIGN__TRP

Bit 3: UNALIGN_ TRP.

DIV_0_TRP

Bit 4: DIV_0_TRP.

BFHFNMIGN

Bit 8: BFHFNMIGN.

STKALIGN

Bit 9: STKALIGN.

SHPR1

System handler priority registers

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								PRI_6 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PRI_5 rw								PRI_4 rw

Toggle Fields.

PRI_4

Bits 0-7: Priority of system handler 4.

PRI_5

Bits 8-15: Priority of system handler 5.

PRI_6

Bits 16-23: Priority of system handler 6.

SHPR2

System handler priority registers

Offset: 0x1C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_11 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

PRI_11

Bits 24-31: Priority of system handler 11.

SHPR3

System handler priority registers

Offset: 0x20, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
PRI_15 rw								PRI_14 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

PRI_14

Bits 16-23: Priority of system handler 14.

PRI_15

Bits 24-31: Priority of system handler 15.

SHCRS

System handler control and state register

Offset: 0x24, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
													USGFAULTENA rw	BUSFAULTENA rw	MEMFAULTENA rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SVCALLPENDED rw	BUSFAULTPENDED rw	MEMFAULTPENDED rw	USGFAULTPENDED rw	SYSTICKACT rw	PENDSVACT rw		MONITORACT rw	SVCALLACT rw				USGFAULTACT rw		BUSFAULTACT rw	MEMFAULTACT rw

Toggle Fields.

MEMFAULTACT

Bit 0: Memory management fault exception active bit.

BUSFAULTACT

Bit 1: Bus fault exception active bit.

USGFAULTACT

Bit 3: Usage fault exception active bit.

SVCALLACT

Bit 7: SVC call active bit.

MONITORACT

Bit 8: Debug monitor active bit.

PENDSVACT

Bit 10: PendSV exception active bit.

SYSTICKACT

Bit 11: SysTick exception active bit.

USGFAULTPENDED

Bit 12: Usage fault exception pending bit.

MEMFAULTPENDED

Bit 13: Memory management fault exception pending bit.

BUSFAULTPENDED

Bit 14: Bus fault exception pending bit.

SVCALLPENDED

Bit 15: SVC call pending bit.

MEMFAULTENA

Bit 16: Memory management fault enable bit.

BUSFAULTENA

Bit 17: Bus fault enable bit.

USGFAULTENA

Bit 18: Usage fault enable bit.

CFSR_UFSR_BFSR_MMFSR

Configurable fault status register

Offset: 0x28, reset: 0x00000000, access: read-write

0/18 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						DIVBYZERO rw	UNALIGNED rw					NOCP rw	INVPC rw	INVSTATE rw	UNDEFINSTR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BFARVALID rw		LSPERR rw	STKERR rw	UNSTKERR rw	IMPRECISERR rw	PRECISERR rw	IBUSERR rw	MMARVALID rw		MLSPERR rw	MSTKERR rw	MUNSTKERR rw		IACCVIOL rw

Toggle Fields.

IACCVIOL

Bit 1: Instruction access violation flag.

MUNSTKERR

Bit 3: Memory manager fault on unstacking for a return from exception.

MSTKERR

Bit 4: Memory manager fault on stacking for exception entry..

MLSPERR

Bit 5: MLSPERR.

MMARVALID

Bit 7: Memory Management Fault Address Register (MMAR) valid flag.

IBUSERR

Bit 8: Instruction bus error.

PRECISERR

Bit 9: Precise data bus error.

IMPRECISERR

Bit 10: Imprecise data bus error.

UNSTKERR

Bit 11: Bus fault on unstacking for a return from exception.

STKERR

Bit 12: Bus fault on stacking for exception entry.

LSPERR

Bit 13: Bus fault on floating-point lazy state preservation.

BFARVALID

Bit 15: Bus Fault Address Register (BFAR) valid flag.

UNDEFINSTR

Bit 16: Undefined instruction usage fault.

INVSTATE

Bit 17: Invalid state usage fault.

INVPC

Bit 18: Invalid PC load usage fault.

NOCP

Bit 19: No coprocessor usage fault..

UNALIGNED

Bit 24: Unaligned access usage fault.

DIVBYZERO

Bit 25: Divide by zero usage fault.

HFSR

Hard fault status register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
DEBUG_VT rw	FORCED rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														VECTTBL rw

Toggle Fields.

VECTTBL

Bit 1: Vector table hard fault.

FORCED

Bit 30: Forced hard fault.

DEBUG_VT

Bit 31: Reserved for Debug use.

MMFAR

Memory management fault address register

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
MMFAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MMFAR rw

Toggle Fields.

MMFAR

Bits 0-31: Memory management fault address.

BFAR

Bus fault address register

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BFAR rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BFAR rw

Toggle Fields.

BFAR

Bits 0-31: Bus fault address.

AFSR

Auxiliary fault status register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
IMPDEF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IMPDEF rw

Toggle Fields.

IMPDEF

Bits 0-31: Implementation defined.

SCB_ACTRL

0xE000E008: System control block ACTLR

0/5 fields covered. Toggle Registers.

ACTRL

Auxiliary control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						DISOOFP rw	DISFPCA rw						DISFOLD rw	DISDEFWBUF rw	DISMCYCINT rw

Toggle Fields.

DISMCYCINT

Bit 0: DISMCYCINT.

DISDEFWBUF

Bit 1: DISDEFWBUF.

DISFOLD

Bit 2: DISFOLD.

DISFPCA

Bit 8: DISFPCA.

DISOOFP

Bit 9: DISOOFP.

SPI1

0x40013000: Serial peripheral interface/Inter-IC sound

10/39 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle Fields.

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x00000700, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x00000002, access: Unspecified

8/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		TIFRFE r	BSY r	OVR r	MODF r	CRCERR rw			TXE r	RXNE r

Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle Fields.

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x00000007, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

SPI2

0x40003800: Serial peripheral interface/Inter-IC sound

10/39 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BIDIMODE rw	BIDIOE rw	CRCEN rw	CRCNEXT rw	DFF rw	RXONLY rw	SSM rw	SSI rw	LSBFIRST rw	SPE rw	BR rw			MSTR rw	CPOL rw	CPHA rw

Toggle Fields.

CPHA

Bit 0: Clock phase.

CPOL

Bit 1: Clock polarity.

MSTR

Bit 2: Master selection.

BR

Bits 3-5: Baud rate control.

SPE

Bit 6: SPI enable.

LSBFIRST

Bit 7: Frame format.

SSI

Bit 8: Internal slave select.

SSM

Bit 9: Software slave management.

RXONLY

Bit 10: Receive only.

DFF

Bit 11: Data frame format.

CRCNEXT

Bit 12: CRC transfer next.

CRCEN

Bit 13: Hardware CRC calculation enable.

BIDIOE

Bit 14: Output enable in bidirectional mode.

BIDIMODE

Bit 15: Bidirectional data mode enable.

CR2

control register 2

Offset: 0x4, reset: 0x00000700, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	LDMA_TX rw	LDMA_RX rw	FRXTH rw	DS rw				TXEIE rw	RXNEIE rw	ERRIE rw	FRF rw	NSSP rw	SSOE rw	TXDMAEN rw	RXDMAEN rw

Toggle Fields.

RXDMAEN

Bit 0: Rx buffer DMA enable.

TXDMAEN

Bit 1: Tx buffer DMA enable.

SSOE

Bit 2: SS output enable.

NSSP

Bit 3: NSS pulse management.

FRF

Bit 4: Frame format.

ERRIE

Bit 5: Error interrupt enable.

RXNEIE

Bit 6: RX buffer not empty interrupt enable.

TXEIE

Bit 7: Tx buffer empty interrupt enable.

DS

Bits 8-11: Data size.

FRXTH

Bit 12: FIFO reception threshold.

LDMA_RX

Bit 13: Last DMA transfer for reception.

LDMA_TX

Bit 14: Last DMA transfer for transmission.

SR

status register

Offset: 0x8, reset: 0x00000002, access: Unspecified

8/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			FTLVL r		FRLVL r		TIFRFE r	BSY r	OVR r	MODF r	CRCERR rw			TXE r	RXNE r

Toggle Fields.

RXNE

Bit 0: Receive buffer not empty.

TXE

Bit 1: Transmit buffer empty.

CRCERR

Bit 4: CRC error flag.

MODF

Bit 5: Mode fault.

OVR

Bit 6: Overrun flag.

BSY

Bit 7: Busy flag.

TIFRFE

Bit 8: TI frame format error.

FRLVL

Bits 9-10: FIFO reception level.

FTLVL

Bits 11-12: FIFO transmission level.

DR

data register

Offset: 0xC, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DR rw

Toggle Fields.

DR

Bits 0-15: Data register.

CRCPR

CRC polynomial register

Offset: 0x10, reset: 0x00000007, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CRCPOLY rw

Toggle Fields.

CRCPOLY

Bits 0-15: CRC polynomial register.

RXCRCR

RX CRC register

Offset: 0x14, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RxCRC r

Toggle Fields.

RxCRC

Bits 0-15: Rx CRC register.

TXCRCR

TX CRC register

Offset: 0x18, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TxCRC r

Toggle Fields.

TxCRC

Bits 0-15: Tx CRC register.

STK

0xE000E010: SysTick timer

0/9 fields covered. Toggle Registers.

CTRL

SysTick control and status register

Offset: 0x0, reset: 0X00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															COUNTFLAG rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													CLKSOURCE rw	TICKINT rw	ENABLE rw

Toggle Fields.

ENABLE

Bit 0: Counter enable.

TICKINT

Bit 1: SysTick exception request enable.

CLKSOURCE

Bit 2: Clock source selection.

COUNTFLAG

Bit 16: COUNTFLAG.

LOAD

SysTick reload value register

Offset: 0x4, reset: 0X00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								RELOAD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RELOAD rw

Toggle Fields.

RELOAD

Bits 0-23: RELOAD value.

VAL

SysTick current value register

Offset: 0x8, reset: 0X00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								CURRENT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CURRENT rw

Toggle Fields.

CURRENT

Bits 0-23: Current counter value.

CALIB

SysTick calibration value register

Offset: 0xC, reset: 0X00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
NOREF rw	SKEW rw							TENMS rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TENMS rw

Toggle Fields.

TENMS

Bits 0-23: Calibration value.

SKEW

Bit 30: SKEW flag: Indicates whether the TENMS value is exact.

NOREF

Bit 31: NOREF flag. Reads as zero.

SYSCFG

0x40010100: System configuration controller

1/149 fields covered. Toggle Registers.

MEMRMP

memory remap register

Offset: 0x0, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
													MEM_MODE rw

Toggle Fields.

MEM_MODE

Bits 0-2: Memory mapping selection.

CFGR1

configuration register 1

Offset: 0x4, reset: 0x7C000001, access: read-write

0/8 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
FPU_IE rw									I2C3_FMP rw		I2C1_FMP rw	I2C_PB9_FMP rw	I2C_PB8_FMP rw	I2C_PB7_FMP rw	I2C_PB6_FMP rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							BOOSTEN rw

Toggle Fields.

BOOSTEN

Bit 8: I/O analog switch voltage booster enable.

I2C_PB6_FMP

Bit 16: Fast-mode Plus (Fm+) driving capability activation on PB6.

I2C_PB7_FMP

Bit 17: Fast-mode Plus (Fm+) driving capability activation on PB7.

I2C_PB8_FMP

Bit 18: Fast-mode Plus (Fm+) driving capability activation on PB8.

I2C_PB9_FMP

Bit 19: Fast-mode Plus (Fm+) driving capability activation on PB9.

I2C1_FMP

Bit 20: I2C1 Fast-mode Plus driving capability activation.

I2C3_FMP

Bit 22: I2C3 Fast-mode Plus driving capability activation.

FPU_IE

Bits 26-31: Floating Point Unit interrupts enable bits.

EXTICR1

external interrupt configuration register 1

Offset: 0x8, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EXTI3 rw				EXTI2 rw				EXTI1 rw				EXTI0 rw

Toggle Fields.

EXTI0

Bits 0-2: EXTI 0 configuration bits.

EXTI1

Bits 4-6: EXTI 1 configuration bits.

EXTI2

Bits 8-10: EXTI 2 configuration bits.

EXTI3

Bits 12-14: EXTI 3 configuration bits.

EXTICR2

external interrupt configuration register 2

Offset: 0xC, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EXTI7 rw				EXTI6 rw				EXTI5 rw				EXTI4 rw

Toggle Fields.

EXTI4

Bits 0-2: EXTI 4 configuration bits.

EXTI5

Bits 4-6: EXTI 5 configuration bits.

EXTI6

Bits 8-10: EXTI 6 configuration bits.

EXTI7

Bits 12-14: EXTI 7 configuration bits.

EXTICR3

external interrupt configuration register 3

Offset: 0x10, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EXTI11 rw				EXTI10 rw				EXTI9 rw				EXTI8 rw

Toggle Fields.

EXTI8

Bits 0-2: EXTI 8 configuration bits.

EXTI9

Bits 4-6: EXTI 9 configuration bits.

EXTI10

Bits 8-10: EXTI 10 configuration bits.

EXTI11

Bits 12-14: EXTI 11 configuration bits.

EXTICR4

external interrupt configuration register 4

Offset: 0x14, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	EXTI15 rw				EXTI14 rw				EXTI13 rw				EXTI12 rw

Toggle Fields.

EXTI12

Bits 0-2: EXTI12 configuration bits.

EXTI13

Bits 4-6: EXTI13 configuration bits.

EXTI14

Bits 8-10: EXTI14 configuration bits.

EXTI15

Bits 12-14: EXTI15 configuration bits.

SCSR

Offset: 0x18, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
C2RFD rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														SRAM2BSY r	SRAM2ER rw

Toggle Fields.

SRAM2ER

Bit 0: SRAM2 Erase.

SRAM2BSY

Bit 1: SRAM2 busy by erase operation.

C2RFD

Bit 31: CPU2 SRAM fetch (execution) disable..

CFGR2

Offset: 0x1C, reset: 0x00000000, access: Unspecified

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							SPF rw					ECCL w	PVDL w	SPL w	CLL w

Toggle Fields.

CLL

Bit 0: Cortex-M4 LOCKUP (Hardfault) output enable bit.

SPL

Bit 1: SRAM2 parity lock bit.

PVDL

Bit 2: PVD lock enable bit.

ECCL

Bit 3: ECC Lock.

SPF

Bit 8: SRAM2 parity error flag.

SWPR

SRAM2 write protection register

Offset: 0x20, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
P31WP w	P30WP w	P29WP w	P28WP w	P27WP w	P26WP w	P25WP w	P24WP w	P23WP w	P22WP w	P21WP w	P20WP w	P19WP w	P18WP w	P17WP w	P16WP w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P15WP w	P14WP w	P13WP w	P12WP w	P11WP w	P10WP w	P9WP w	P8WP w	P7WP w	P6WP w	P5WP w	P4WP w	P3WP w	P2WP w	P1WP w	P0WP w

Toggle Fields.

P0WP

Bit 0: P0WP.

P1WP

Bit 1: P1WP.

P2WP

Bit 2: P2WP.

P3WP

Bit 3: P3WP.

P4WP

Bit 4: P4WP.

P5WP

Bit 5: P5WP.

P6WP

Bit 6: P6WP.

P7WP

Bit 7: P7WP.

P8WP

Bit 8: P8WP.

P9WP

Bit 9: P9WP.

P10WP

Bit 10: P10WP.

P11WP

Bit 11: P11WP.

P12WP

Bit 12: P12WP.

P13WP

Bit 13: P13WP.

P14WP

Bit 14: P14WP.

P15WP

Bit 15: P15WP.

P16WP

Bit 16: P16WP.

P17WP

Bit 17: P17WP.

P18WP

Bit 18: P18WP.

P19WP

Bit 19: P19WP.

P20WP

Bit 20: P20WP.

P21WP

Bit 21: P21WP.

P22WP

Bit 22: P22WP.

P23WP

Bit 23: P23WP.

P24WP

Bit 24: P24WP.

P25WP

Bit 25: P25WP.

P26WP

Bit 26: P26WP.

P27WP

Bit 27: P27WP.

P28WP

Bit 28: P28WP.

P29WP

Bit 29: P29WP.

P30WP

Bit 30: P30WP.

P31WP

Bit 31: SRAM2 page 31 write protection.

SKR

Offset: 0x24, reset: 0x00000000, access: write-only

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								KEY w

Toggle Fields.

KEY

Bits 0-7: SRAM2 write protection key for software erase.

SWPR2

SRAM2 write protection register 2

Offset: 0x28, reset: 0x00000000, access: write-only

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
P63WP w	P62WP w	P61WP w	P60WP w	P59WP w	P58WP w	P57WP w	P56WP w	P55WP w	P54WP w	P53WP w	P52WP w	P51WP w	P50WP w	P49WP w	P48WP w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
P47WP w	P46WP w	P45WP w	P44WP w	P43WP w	P42WP w	P41WP w	P40WP w	P39WP w	P38WP w	P37WP w	P36WP w	P35WP w	P34WP w	P33WP w	P32WP w

Toggle Fields.

P32WP

Bit 0: P32WP.

P33WP

Bit 1: P33WP.

P34WP

Bit 2: P34WP.

P35WP

Bit 3: P35WP.

P36WP

Bit 4: P36WP.

P37WP

Bit 5: P37WP.

P38WP

Bit 6: P38WP.

P39WP

Bit 7: P39WP.

P40WP

Bit 8: P40WP.

P41WP

Bit 9: P41WP.

P42WP

Bit 10: P42WP.

P43WP

Bit 11: P43WP.

P44WP

Bit 12: P44WP.

P45WP

Bit 13: P45WP.

P46WP

Bit 14: P46WP.

P47WP

Bit 15: P47WP.

P48WP

Bit 16: P48WP.

P49WP

Bit 17: P49WP.

P50WP

Bit 18: P50WP.

P51WP

Bit 19: P51WP.

P52WP

Bit 20: P52WP.

P53WP

Bit 21: P53WP.

P54WP

Bit 22: P54WP.

P55WP

Bit 23: P55WP.

P56WP

Bit 24: P56WP.

P57WP

Bit 25: P57WP.

P58WP

Bit 26: P58WP.

P59WP

Bit 27: P59WP.

P60WP

Bit 28: P60WP.

P61WP

Bit 29: P61WP.

P62WP

Bit 30: P62WP.

P63WP

Bit 31: SRAM2 page 63 write protection.

IMR1

CPU1 interrupt mask register 1

Offset: 0x2C, reset: 0x00000000, access: read-write

0/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
EXIT15IM rw	EXIT14IM rw	EXIT13IM rw	EXIT12IM rw	EXIT11IM rw	EXIT10IM rw	EXIT9IM rw	EXIT8IM rw	EXIT7IM rw	EXIT6IM rw	EXIT5IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
TIM17IM rw	TIM16IM rw	TIM1IM rw

Toggle Fields.

TIM1IM

Bit 13: Peripheral TIM1 interrupt mask to CPU1.

TIM16IM

Bit 14: Peripheral TIM16 interrupt mask to CPU1.

TIM17IM

Bit 15: Peripheral TIM17 interrupt mask to CPU1.

EXIT5IM

Bit 21: Peripheral EXIT5 interrupt mask to CPU1.

EXIT6IM

Bit 22: Peripheral EXIT6 interrupt mask to CPU1.

EXIT7IM

Bit 23: Peripheral EXIT7 interrupt mask to CPU1.

EXIT8IM

Bit 24: Peripheral EXIT8 interrupt mask to CPU1.

EXIT9IM

Bit 25: Peripheral EXIT9 interrupt mask to CPU1.

EXIT10IM

Bit 26: Peripheral EXIT10 interrupt mask to CPU1.

EXIT11IM

Bit 27: Peripheral EXIT11 interrupt mask to CPU1.

EXIT12IM

Bit 28: Peripheral EXIT12 interrupt mask to CPU1.

EXIT13IM

Bit 29: Peripheral EXIT13 interrupt mask to CPU1.

EXIT14IM

Bit 30: Peripheral EXIT14 interrupt mask to CPU1.

EXIT15IM

Bit 31: Peripheral EXIT15 interrupt mask to CPU1.

IMR2

CPU1 interrupt mask register 2

Offset: 0x30, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											PVDIM rw		PVM3IM rw		PVM1IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Toggle Fields.

PVM1IM

Bit 16: Peripheral PVM1 interrupt mask to CPU1.

PVM3IM

Bit 18: Peripheral PVM3 interrupt mask to CPU1.

PVDIM

Bit 20: Peripheral PVD interrupt mask to CPU1.

C2IMR1

CPU2 interrupt mask register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			ADC rw	COMP rw	AES1 rw	RNG rw	PKA rw		FLASH rw	RCC rw	RTCALARM rw	RTCWKUP rw			RTCSTAMP rw

Toggle Fields.

RTCSTAMP

Bit 0: Peripheral RTCSTAMP interrupt mask to CPU2.

RTCWKUP

Bit 3: Peripheral RTCWKUP interrupt mask to CPU2.

RTCALARM

Bit 4: Peripheral RTCALARM interrupt mask to CPU2.

RCC

Bit 5: Peripheral RCC interrupt mask to CPU2.

FLASH

Bit 6: Peripheral FLASH interrupt mask to CPU2.

PKA

Bit 8: Peripheral PKA interrupt mask to CPU2.

RNG

Bit 9: Peripheral RNG interrupt mask to CPU2.

AES1

Bit 10: Peripheral AES1 interrupt mask to CPU2.

COMP

Bit 11: Peripheral COMP interrupt mask to CPU2.

ADC

Bit 12: Peripheral ADC interrupt mask to CPU2.

C2IMR2

CPU2 interrupt mask register 1

Offset: 0x38, reset: 0x00000000, access: read-write

0/20 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									LCDIM rw	TSCIM rw	PVDIM rw		PVM3IM rw		PVM1IM rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAM_UX1_IM rw	DMA2_CH7_IM rw	DMA2_CH6_IM rw	DMA2_CH5_IM rw	DMA2_CH4_IM rw	DMA2_CH3_IM rw	DMA2_CH2_IM rw	DMA2_CH1_IM rw		DMA1_CH7_IM rw	DMA1_CH6_IM rw	DMA1_CH5_IM rw	DMA1_CH4_IM rw	DMA1_CH3_IM rw	DMA1_CH2_IM rw	DMA1_CH1_IM rw

Toggle Fields.

DMA1_CH1_IM

Bit 0: Peripheral DMA1 CH1 interrupt mask to CPU2.

DMA1_CH2_IM

Bit 1: Peripheral DMA1 CH2 interrupt mask to CPU2.

DMA1_CH3_IM

Bit 2: Peripheral DMA1 CH3 interrupt mask to CPU2.

DMA1_CH4_IM

Bit 3: Peripheral DMA1 CH4 interrupt mask to CPU2.

DMA1_CH5_IM

Bit 4: Peripheral DMA1 CH5 interrupt mask to CPU2.

DMA1_CH6_IM

Bit 5: Peripheral DMA1 CH6 interrupt mask to CPU2.

DMA1_CH7_IM

Bit 6: Peripheral DMA1 CH7 interrupt mask to CPU2.

DMA2_CH1_IM

Bit 8: Peripheral DMA2 CH1 interrupt mask to CPU1.

DMA2_CH2_IM

Bit 9: Peripheral DMA2 CH2 interrupt mask to CPU1.

DMA2_CH3_IM

Bit 10: Peripheral DMA2 CH3 interrupt mask to CPU1.

DMA2_CH4_IM

Bit 11: Peripheral DMA2 CH4 interrupt mask to CPU1.

DMA2_CH5_IM

Bit 12: Peripheral DMA2 CH5 interrupt mask to CPU1.

DMA2_CH6_IM

Bit 13: Peripheral DMA2 CH6 interrupt mask to CPU1.

DMA2_CH7_IM

Bit 14: Peripheral DMA2 CH7 interrupt mask to CPU1.

DMAM_UX1_IM

Bit 15: Peripheral DMAM UX1 interrupt mask to CPU1.

PVM1IM

Bit 16: Peripheral PVM1IM interrupt mask to CPU1.

PVM3IM

Bit 18: Peripheral PVM3IM interrupt mask to CPU1.

PVDIM

Bit 20: Peripheral PVDIM interrupt mask to CPU1.

TSCIM

Bit 21: Peripheral TSCIM interrupt mask to CPU1.

LCDIM

Bit 22: Peripheral LCDIM interrupt mask to CPU1.

SIPCR

secure IP control register

Offset: 0x3C, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												SRNG rw	SPKA rw	SAES2 rw	SAES1 rw

Toggle Fields.

SAES1

Bit 0: Enable AES1 KEY[7:0] security..

SAES2

Bit 1: Enable AES2 security..

SPKA

Bit 2: Enable PKA security.

SRNG

Bit 3: Enable True RNG security.

TIM1

0x40012C00: Advanced-timers

1/183 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields.

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
								MMS2 rw					OIS6 rw		OIS5 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	OIS4 rw	OIS3N rw	OIS3 rw	OIS2N rw	OIS2 rw	OIS1N rw	OIS1 rw	TI1S rw	MMS rw			CCDS rw	CCUS rw		CCPC rw

Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

OIS2

Bit 10: Output Idle state 2.

OIS2N

Bit 11: Output Idle state 2.

OIS3

Bit 12: Output Idle state 3.

OIS3N

Bit 13: Output Idle state 3.

OIS4

Bit 14: Output Idle state 4.

OIS5

Bit 16: Output Idle state 5 (OC5 output).

OIS6

Bit 18: Output Idle state 6 (OC6 output).

MMS2

Bits 20-23: Master mode selection 2.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
	TDE rw	COMDE rw	CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw	BIE rw	TIE rw	COMIE rw	CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle Fields.

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

COMIE

Bit 5: COM interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

BIE

Bit 7: Break interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

COMDE

Bit 13: COM DMA request enable.

TDE

Bit 14: Trigger DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/16 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
														CC6IF rw	CC5IF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		SBIF rw	CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw	B2IF rw	BIF rw	TIF rw	COMIF rw	CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle Fields.

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

B2IF

Bit 8: Break 2 interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

SBIF

Bit 13: System Break interrupt flag.

CC5IF

Bit 16: Compare 5 interrupt flag.

CC6IF

Bit 17: Compare 6 interrupt flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							B2G w	BG w	TG w	COMG w	CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle Fields.

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

B2G

Bit 8: Break 2 generation.

CCMR1_Output

capture/compare mode register 1 (output mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC2M_3 rw								OC1M_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC2CE rw	OC2M rw			OC2PE rw	OC2FE rw	CC2S rw		OC1CE rw	OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1CE

Bit 7: Output Compare 1 clear enable.

CC2S

Bits 8-9: Capture/Compare 2 selection.

OC2FE

Bit 10: Output Compare 2 fast enable.

OC2PE

Bit 11: Output Compare 2 preload enable.

OC2M

Bits 12-14: Output Compare 2 mode.

OC2CE

Bit 15: Output Compare 2 clear enable.

OC1M_3

Bit 16: Output Compare 1 mode - bit 3.

OC2M_3

Bit 24: Output Compare 2 mode - bit 3.

CCMR2_Input

capture/compare mode register 2 (output mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				C3PSC rw		CC3S rw

Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

C3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/19 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
										CC6P rw	CC6E rw			CC5P rw	CC5E rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw	CC3NE rw	CC3P rw	CC3E rw	CC2NP rw	CC2NE rw	CC2P rw	CC2E rw	CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NE

Bit 6: Capture/Compare 2 complementary output enable.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NE

Bit 10: Capture/Compare 3 complementary output enable.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 complementary output polarity.

CC5E

Bit 16: Capture/Compare 5 output enable.

CC5P

Bit 17: Capture/Compare 5 output polarity.

CC6E

Bit 20: Capture/Compare 6 output enable.

CC6P

Bit 21: Capture/Compare 6 output polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields.

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x0000FFFF, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
REP rw

Toggle Fields.

REP

Bits 0-15: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2 rw

Toggle Fields.

CCR2

Bits 0-15: Capture/Compare 2 value.

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3 rw

Toggle Fields.

CCR3

Bits 0-15: Capture/Compare value.

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4 rw

Toggle Fields.

CCR4

Bits 0-15: Capture/Compare value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
						BK2P rw	BK2E rw	BK2F rw				BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

BK2F

Bits 20-23: Break 2 filter.

BK2E

Bit 24: Break 2 enable.

BK2P

Bit 25: Break 2 polarity.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR

DMA address for full transfer

Offset: 0x50, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TI1_RMP rw			TIM1_ETR_ADC1_RMP rw

Toggle Fields.

TIM1_ETR_ADC1_RMP

Bits 0-1: TIM1_ETR_ADC1 remapping capability.

TI1_RMP

Bit 4: Input Capture 1 remap.

CCMR3_Output

capture/compare mode register 2 (output mode)

Offset: 0x54, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
							OC6M_bit3 rw								OC5M_bit3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OC6CE rw	OC6M rw			OC6PE rw	OC6FE rw			OC5CE rw	OC5M rw			OC5PE rw	OC5FE rw

Toggle Fields.

OC5FE

Bit 2: Output compare 5 fast enable.

OC5PE

Bit 3: Output compare 5 preload enable.

OC5M

Bits 4-6: Output compare 5 mode.

OC5CE

Bit 7: Output compare 5 clear enable.

OC6FE

Bit 10: Output compare 6 fast enable.

OC6PE

Bit 11: Output compare 6 preload enable.

OC6M

Bits 12-14: Output compare 6 mode.

OC6CE

Bit 15: Output compare 6 clear enable.

OC5M_bit3

Bit 16: Output Compare 5 mode bit 3.

OC6M_bit3

Bit 24: Output Compare 6 mode bit 3.

CCR5

capture/compare register 4

Offset: 0x58, reset: 0x00000000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
GC5C3 rw	GC5C2 rw	GC5C1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR5 rw

Toggle Fields.

CCR5

Bits 0-15: Capture/Compare value.

GC5C1

Bit 29: Group Channel 5 and Channel 1.

GC5C2

Bit 30: Group Channel 5 and Channel 2.

GC5C3

Bit 31: Group Channel 5 and Channel 3.

CCR6

capture/compare register 4

Offset: 0x5C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR6 rw

Toggle Fields.

CCR6

Bits 0-15: Capture/Compare value.

AF1

DMA address for full transfer

Offset: 0x60, reset: 0x00000001, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarity.

ETRSEL

Bits 14-16: ETR source selection.

AF2

DMA address for full transfer

Offset: 0x64, reset: 0x00000001, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BK2CMP2P rw	BK2CMP1P rw	BK2INP rw	BK2DFBK0E rw						BK2CMP2E rw	BK2CMP1E rw	BK2INE rw

Toggle Fields.

BK2INE

Bit 0: BRK2 BKIN input enable.

BK2CMP1E

Bit 1: BRK2 COMP1 enable.

BK2CMP2E

Bit 2: BRK2 COMP2 enable.

BK2DFBK0E

Bit 8: BRK2 DFSDM_BREAK0 enable.

BK2INP

Bit 9: BRK2 BKIN input polarity.

BK2CMP1P

Bit 10: BRK2 COMP1 input polarity.

BK2CMP2P

Bit 11: BRK2 COMP2 input polarity.

TIM16

0x40014400: General purpose timers

1/65 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw	TIF rw	COMIF rw				CC1IF rw	UIF rw

Toggle Fields.

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w				CC1G w	UG w

Toggle Fields.

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields.

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x30, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x44, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM16 option register 1

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TI1_RMP rw

Toggle Fields.

TI1_RMP

Bits 0-1: Input capture 1 remap.

AF1

TIM17 option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM17

0x40014800: General purpose timers

1/66 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/7 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw				OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields.

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						OIS1N rw	OIS1 rw					CCDS rw	CCUS rw		CCPC rw

Toggle Fields.

CCPC

Bit 0: Capture/compare preloaded control.

CCUS

Bit 2: Capture/compare control update selection.

CCDS

Bit 3: Capture/compare DMA selection.

OIS1

Bit 8: Output Idle state 1.

OIS1N

Bit 9: Output Idle state 1.

DIER

DMA/Interrupt enable register

Offset: 0x8, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

SR

status register

Offset: 0xC, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						CC1OF rw		BIF rw	TIF rw	COMIF rw				CC1IF rw	UIF rw

Toggle Fields.

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

COMIF

Bit 5: COM interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

BIF

Bit 7: Break interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

EGR

event generation register

Offset: 0x10, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BG w	TG w	COMG w				CC1G w	UG w

Toggle Fields.

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

COMG

Bit 5: Capture/Compare control update generation.

TG

Bit 6: Trigger generation.

BG

Bit 7: Break generation.

CCMR1_Output

capture/compare mode register (output mode)

Offset: 0x14, reset: 0x00000000, access: read-write

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															OC1M_2 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									OC1M rw			OC1PE rw	OC1FE rw	CC1S rw

Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

OC1FE

Bit 2: Output Compare 1 fast enable.

OC1PE

Bit 3: Output Compare 1 preload enable.

OC1M

Bits 4-6: Output Compare 1 mode.

OC1M_2

Bit 16: Output Compare 1 mode.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								IC1F rw				IC1PSC rw		CC1S rw

Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CCER

capture/compare enable register

Offset: 0x1C, reset: 0x0000, access: read-write

0/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												CC1NP rw	CC1NE rw	CC1P rw	CC1E rw

Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NE

Bit 2: Capture/Compare 1 complementary output enable.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CNT

counter

Offset: 0x20, reset: 0x00000000, access: Unspecified

1/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT rw

Toggle Fields.

CNT

Bits 0-15: counter value.

UIFCPY

Bit 31: UIF Copy.

PSC

prescaler

Offset: 0x24, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x28, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR rw

Toggle Fields.

ARR

Bits 0-15: Auto-reload value.

RCR

repetition counter register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								REP rw

Toggle Fields.

REP

Bits 0-7: Repetition counter value.

CCR1

capture/compare register 1

Offset: 0x30, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1 rw

Toggle Fields.

CCR1

Bits 0-15: Capture/Compare 1 value.

BDTR

break and dead-time register

Offset: 0x34, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
												BKF rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
MOE rw	AOE rw	BKP rw	BKE rw	OSSR rw	OSSI rw	LOCK rw		DTG rw

Toggle Fields.

DTG

Bits 0-7: Dead-time generator setup.

LOCK

Bits 8-9: Lock configuration.

OSSI

Bit 10: Off-state selection for Idle mode.

OSSR

Bit 11: Off-state selection for Run mode.

BKE

Bit 12: Break enable.

BKP

Bit 13: Break polarity.

AOE

Bit 14: Automatic output enable.

MOE

Bit 15: Main output enable.

BKF

Bits 16-19: Break filter.

DCR

DMA control register

Offset: 0x38, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x3C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM16 option register 1

Offset: 0x40, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														TI1_RMP rw

Toggle Fields.

TI1_RMP

Bits 0-1: Input capture 1 remap.

AF1

TIM17 option register 1

Offset: 0x44, reset: 0x0000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				BKCMP2P rw	BKCMP1P rw	BKINP rw							BKCMP2E rw	BKCMP1E rw	BKINE rw

Toggle Fields.

BKINE

Bit 0: BRK BKIN input enable.

BKCMP1E

Bit 1: BRK COMP1 enable.

BKCMP2E

Bit 2: BRK COMP2 enable.

BKINP

Bit 9: BRK BKIN input polarity.

BKCMP1P

Bit 10: BRK COMP1 input polarity.

BKCMP2P

Bit 11: BRK COMP2 input polarit.

TIM2

0x40000000: General-purpose-timers

1/117 fields covered. Toggle Registers.

CR1

control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
				UIFREMAP rw		CKD rw		ARPE rw	CMS rw		DIR rw	OPM rw	URS rw	UDIS rw	CEN rw

Toggle Fields.

CEN

Bit 0: Counter enable.

UDIS

Bit 1: Update disable.

URS

Bit 2: Update request source.

OPM

Bit 3: One-pulse mode.

DIR

Bit 4: Direction.

CMS

Bits 5-6: Center-aligned mode selection.

ARPE

Bit 7: Auto-reload preload enable.

CKD

Bits 8-9: Clock division.

UIFREMAP

Bit 11: UIF status bit remapping.

CR2

control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								TI1S rw	MMS rw			CCDS rw

Toggle Fields.

CCDS

Bit 3: Capture/compare DMA selection.

MMS

Bits 4-6: Master mode selection.

TI1S

Bit 7: TI1 selection.

SMCR

slave mode control register

Offset: 0x8, reset: 0x0000, access: read-write

0/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															SMS_3 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETP rw	ECE rw	ETPS rw		ETF rw				MSM rw	TS rw			OCCS rw	SMS rw

Toggle Fields.

SMS

Bits 0-2: Slave mode selection.

OCCS

Bit 3: OCREF clear selection.

TS

Bits 4-6: Trigger selection.

MSM

Bit 7: Master/Slave mode.

ETF

Bits 8-11: External trigger filter.

ETPS

Bits 12-13: External trigger prescaler.

ECE

Bit 14: External clock enable.

ETP

Bit 15: External trigger polarity.

SMS_3

Bit 16: Slave mode selection - bit 3.

DIER

DMA/Interrupt enable register

Offset: 0xC, reset: 0x0000, access: read-write

0/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4DE rw	CC3DE rw	CC2DE rw	CC1DE rw	UDE rw		TIE rw		CC4IE rw	CC3IE rw	CC2IE rw	CC1IE rw	UIE rw

Toggle Fields.

UIE

Bit 0: Update interrupt enable.

CC1IE

Bit 1: Capture/Compare 1 interrupt enable.

CC2IE

Bit 2: Capture/Compare 2 interrupt enable.

CC3IE

Bit 3: Capture/Compare 3 interrupt enable.

CC4IE

Bit 4: Capture/Compare 4 interrupt enable.

TIE

Bit 6: Trigger interrupt enable.

UDE

Bit 8: Update DMA request enable.

CC1DE

Bit 9: Capture/Compare 1 DMA request enable.

CC2DE

Bit 10: Capture/Compare 2 DMA request enable.

CC3DE

Bit 11: Capture/Compare 3 DMA request enable.

CC4DE

Bit 12: Capture/Compare 4 DMA request enable.

SR

status register

Offset: 0x10, reset: 0x0000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			CC4OF rw	CC3OF rw	CC2OF rw	CC1OF rw			TIF rw		CC4IF rw	CC3IF rw	CC2IF rw	CC1IF rw	UIF rw

Toggle Fields.

UIF

Bit 0: Update interrupt flag.

CC1IF

Bit 1: Capture/compare 1 interrupt flag.

CC2IF

Bit 2: Capture/Compare 2 interrupt flag.

CC3IF

Bit 3: Capture/Compare 3 interrupt flag.

CC4IF

Bit 4: Capture/Compare 4 interrupt flag.

TIF

Bit 6: Trigger interrupt flag.

CC1OF

Bit 9: Capture/Compare 1 overcapture flag.

CC2OF

Bit 10: Capture/compare 2 overcapture flag.

CC3OF

Bit 11: Capture/Compare 3 overcapture flag.

CC4OF

Bit 12: Capture/Compare 4 overcapture flag.

EGR

event generation register

Offset: 0x14, reset: 0x0000, access: write-only

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									TG w		CC4G w	CC3G w	CC2G w	CC1G w	UG w

Toggle Fields.

UG

Bit 0: Update generation.

CC1G

Bit 1: Capture/compare 1 generation.

CC2G

Bit 2: Capture/compare 2 generation.

CC3G

Bit 3: Capture/compare 3 generation.

CC4G

Bit 4: Capture/compare 4 generation.

TG

Bit 6: Trigger generation.

CCMR1_Input

capture/compare mode register 1 (input mode)

Offset: 0x18, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC2F rw				IC2PSC rw		CC2S rw		IC1F rw				IC1PSC rw		CC1S rw

Toggle Fields.

CC1S

Bits 0-1: Capture/Compare 1 selection.

IC1PSC

Bits 2-3: Input capture 1 prescaler.

IC1F

Bits 4-7: Input capture 1 filter.

CC2S

Bits 8-9: Capture/compare 2 selection.

IC2PSC

Bits 10-11: Input capture 2 prescaler.

IC2F

Bits 12-15: Input capture 2 filter.

CCMR2_Input

capture/compare mode register 2 (input mode)

Offset: 0x1C, reset: 0x00000000, access: read-write

0/6 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IC4F rw				IC4PSC rw		CC4S rw		IC3F rw				IC3PSC rw		CC3S rw

Toggle Fields.

CC3S

Bits 0-1: Capture/Compare 3 selection.

IC3PSC

Bits 2-3: Input capture 3 prescaler.

IC3F

Bits 4-7: Input capture 3 filter.

CC4S

Bits 8-9: Capture/Compare 4 selection.

IC4PSC

Bits 10-11: Input capture 4 prescaler.

IC4F

Bits 12-15: Input capture 4 filter.

CCER

capture/compare enable register

Offset: 0x20, reset: 0x0000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CC4NP rw		CC4P rw	CC4E rw	CC3NP rw		CC3P rw	CC3E rw	CC2NP rw		CC2P rw	CC2E rw	CC1NP rw		CC1P rw	CC1E rw

Toggle Fields.

CC1E

Bit 0: Capture/Compare 1 output enable.

CC1P

Bit 1: Capture/Compare 1 output Polarity.

CC1NP

Bit 3: Capture/Compare 1 output Polarity.

CC2E

Bit 4: Capture/Compare 2 output enable.

CC2P

Bit 5: Capture/Compare 2 output Polarity.

CC2NP

Bit 7: Capture/Compare 2 output Polarity.

CC3E

Bit 8: Capture/Compare 3 output enable.

CC3P

Bit 9: Capture/Compare 3 output Polarity.

CC3NP

Bit 11: Capture/Compare 3 output Polarity.

CC4E

Bit 12: Capture/Compare 4 output enable.

CC4P

Bit 13: Capture/Compare 3 output Polarity.

CC4NP

Bit 15: Capture/Compare 4 output Polarity.

CNT

counter

Offset: 0x24, reset: 0x00000000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
UIFCPY r	CNT_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CNT_L rw

Toggle Fields.

CNT_L

Bits 0-15: Low counter value.

CNT_H

Bits 16-30: High counter value (TIM2 only).

UIFCPY

Bit 31: Value depends on IUFREMAP in TIM2_CR1..

PSC

prescaler

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PSC rw

Toggle Fields.

PSC

Bits 0-15: Prescaler value.

ARR

auto-reload register

Offset: 0x2C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ARR_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ARR_L rw

Toggle Fields.

ARR_L

Bits 0-15: Low Auto-reload value.

ARR_H

Bits 16-31: High Auto-reload value (TIM2 only).

CCR1

capture/compare register 1

Offset: 0x34, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR1_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR1_L rw

Toggle Fields.

CCR1_L

Bits 0-15: Low Capture/Compare 1 value.

CCR1_H

Bits 16-31: High Capture/Compare 1 value (TIM2 only).

CCR2

capture/compare register 2

Offset: 0x38, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR2_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR2_L rw

Toggle Fields.

CCR2_L

Bits 0-15: Low Capture/Compare 2 value.

CCR2_H

Bits 16-31: High Capture/Compare 2 value (TIM2 only).

CCR3

capture/compare register 3

Offset: 0x3C, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR3_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR3_L rw

Toggle Fields.

CCR3_L

Bits 0-15: Low Capture/Compare value.

CCR3_H

Bits 16-31: High Capture/Compare value (TIM2 only).

CCR4

capture/compare register 4

Offset: 0x40, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CCR4_H rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CCR4_L rw

Toggle Fields.

CCR4_L

Bits 0-15: Low Capture/Compare value.

CCR4_H

Bits 16-31: High Capture/Compare value (TIM2 only).

DCR

DMA control register

Offset: 0x48, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
			DBL rw								DBA rw

Toggle Fields.

DBA

Bits 0-4: DMA base address.

DBL

Bits 8-12: DMA burst length.

DMAR

DMA address for full transfer

Offset: 0x4C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DMAB rw

Toggle Fields.

DMAB

Bits 0-15: DMA register for burst accesses.

OR

TIM2 option register

Offset: 0x50, reset: 0x0000, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												TI4_RMP rw		ETR_RMP rw	ITR_RMP rw

Toggle Fields.

ITR_RMP

Bit 0: Internal trigger remap.

ETR_RMP

Bit 1: External trigger remap.

TI4_RMP

Bits 2-3: Input capture 4 remap.

AF

TIM2 alternate function option register 1

Offset: 0x60, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
															ETRSEL rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ETRSEL rw

Toggle Fields.

ETRSEL

Bits 14-16: External trigger source selection.

TSC

0x40024000: Touch sensing controller

14/151 fields covered. Toggle Registers.

CR

control register

Offset: 0x0, reset: 0x00000000, access: read-write

0/12 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
CTPH rw				CTPL rw				SSD rw							SSE rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SSPSC rw	PGPSC rw							MCV rw			IODEF rw	SYNCPOL rw	AM rw	START rw	TSCE rw

Toggle Fields.

TSCE

Bit 0: Touch sensing controller enable.

START

Bit 1: Start a new acquisition.

AM

Bit 2: Acquisition mode.

SYNCPOL

Bit 3: Synchronization pin polarity.

IODEF

Bit 4: I/O Default mode.

MCV

Bits 5-7: Max count value.

PGPSC

Bits 12-14: pulse generator prescaler.

SSPSC

Bit 15: Spread spectrum prescaler.

SSE

Bit 16: Spread spectrum enable.

SSD

Bits 17-23: Spread spectrum deviation.

CTPL

Bits 24-27: Charge transfer pulse low.

CTPH

Bits 28-31: Charge transfer pulse high.

IER

interrupt enable register

Offset: 0x4, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEIE rw	EOAIE rw

Toggle Fields.

EOAIE

Bit 0: End of acquisition interrupt enable.

MCEIE

Bit 1: Max count error interrupt enable.

ICR

interrupt clear register

Offset: 0x8, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEIC rw	EOAIC rw

Toggle Fields.

EOAIC

Bit 0: End of acquisition interrupt clear.

MCEIC

Bit 1: Max count error interrupt clear.

ISR

interrupt status register

Offset: 0xC, reset: 0x00000000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
														MCEF rw	EOAF rw

Toggle Fields.

EOAF

Bit 0: End of acquisition flag.

MCEF

Bit 1: Max count error flag.

IOHCR

I/O hysteresis control register

Offset: 0x10, reset: 0xFFFFFFFF, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle Fields.

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

IOASCR

I/O analog switch control register

Offset: 0x18, reset: 0x00000000, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle Fields.

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

IOSCR

I/O sampling control register

Offset: 0x20, reset: 0x00000000, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle Fields.

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

IOCCR

I/O channel control register

Offset: 0x28, reset: 0x00000000, access: read-write

0/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				G7_IO4 rw	G7_IO3 rw	G7_IO2 rw	G7_IO1 rw	G6_IO4 rw	G6_IO3 rw	G6_IO2 rw	G6_IO1 rw	G5_IO4 rw	G5_IO3 rw	G5_IO2 rw	G5_IO1 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
G4_IO4 rw	G4_IO3 rw	G4_IO2 rw	G4_IO1 rw	G3_IO4 rw	G3_IO3 rw	G3_IO2 rw	G3_IO1 rw	G2_IO4 rw	G2_IO3 rw	G2_IO2 rw	G2_IO1 rw	G1_IO4 rw	G1_IO3 rw	G1_IO2 rw	G1_IO1 rw

Toggle Fields.

G1_IO1

Bit 0: G1_IO1.

G1_IO2

Bit 1: G1_IO2.

G1_IO3

Bit 2: G1_IO3.

G1_IO4

Bit 3: G1_IO4.

G2_IO1

Bit 4: G2_IO1.

G2_IO2

Bit 5: G2_IO2.

G2_IO3

Bit 6: G2_IO3.

G2_IO4

Bit 7: G2_IO4.

G3_IO1

Bit 8: G3_IO1.

G3_IO2

Bit 9: G3_IO2.

G3_IO3

Bit 10: G3_IO3.

G3_IO4

Bit 11: G3_IO4.

G4_IO1

Bit 12: G4_IO1.

G4_IO2

Bit 13: G4_IO2.

G4_IO3

Bit 14: G4_IO3.

G4_IO4

Bit 15: G4_IO4.

G5_IO1

Bit 16: G5_IO1.

G5_IO2

Bit 17: G5_IO2.

G5_IO3

Bit 18: G5_IO3.

G5_IO4

Bit 19: G5_IO4.

G6_IO1

Bit 20: G6_IO1.

G6_IO2

Bit 21: G6_IO2.

G6_IO3

Bit 22: G6_IO3.

G6_IO4

Bit 23: G6_IO4.

G7_IO1

Bit 24: G7_IO1.

G7_IO2

Bit 25: G7_IO2.

G7_IO3

Bit 26: G7_IO3.

G7_IO4

Bit 27: G7_IO4.

IOGCSR

I/O group control status register

Offset: 0x30, reset: 0x00000000, access: Unspecified

7/14 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
									G7S r	G6S r	G5S r	G4S r	G3S r	G2S r	G1S r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
									G7E rw	G6E rw	G5E rw	G4E rw	G3E rw	G2E rw	G1E rw

Toggle Fields.

G1E

Bit 0: Analog I/O group x enable.

G2E

Bit 1: Analog I/O group x enable.

G3E

Bit 2: Analog I/O group x enable.

G4E

Bit 3: Analog I/O group x enable.

G5E

Bit 4: Analog I/O group x enable.

G6E

Bit 5: Analog I/O group x enable.

G7E

Bit 6: Analog I/O group x enable.

G1S

Bit 16: Analog I/O group x status.

G2S

Bit 17: Analog I/O group x status.

G3S

Bit 18: Analog I/O group x status.

G4S

Bit 19: Analog I/O group x status.

G5S

Bit 20: Analog I/O group x status.

G6S

Bit 21: Analog I/O group x status.

G7S

Bit 22: Analog I/O group x status.

IOG1CR

I/O group x counter register

Offset: 0x34, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle Fields.

CNT

Bits 0-13: Counter value.

IOG2CR

I/O group x counter register

Offset: 0x38, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle Fields.

CNT

Bits 0-13: Counter value.

IOG3CR

I/O group x counter register

Offset: 0x3C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle Fields.

CNT

Bits 0-13: Counter value.

IOG4CR

I/O group x counter register

Offset: 0x40, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle Fields.

CNT

Bits 0-13: Counter value.

IOG5CR

I/O group x counter register

Offset: 0x44, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle Fields.

CNT

Bits 0-13: Counter value.

IOG6CR

I/O group x counter register

Offset: 0x48, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle Fields.

CNT

Bits 0-13: Counter value.

IOG7CR

I/O group x counter register

Offset: 0x4C, reset: 0x00000000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		CNT r

Toggle Fields.

CNT

Bits 0-13: Counter value.

USART1

0x40013800: Universal synchronous asynchronous receiver transmitter

29/134 fields covered. Toggle Registers.

CR1

Control register 1

Offset: 0x0, reset: 0x0000, access: read-write

0/32 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
RXFFIE rw	TXFEIE rw	FIFOEN rw	M1 rw	EOBIE rw	RTOIE rw	DEAT4 rw	DEAT3 rw	DEAT2 rw	DEAT1 rw	DEAT0 rw	DEDT4 rw	DEDT3 rw	DEDT2 rw	DEDT1 rw	DEDT0 rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OVER8 rw	CMIE rw	MME rw	M0 rw	WAKE rw	PCE rw	PS rw	PEIE rw	TXEIE rw	TCIE rw	RXNEIE rw	IDLEIE rw	TE rw	RE rw	UESM rw	UE rw

Toggle Fields.

UE

Bit 0: USART enable.

UESM

Bit 1: USART enable in Stop mode.

RE

Bit 2: Receiver enable.

TE

Bit 3: Transmitter enable.

IDLEIE

Bit 4: IDLE interrupt enable.

RXNEIE

Bit 5: RXNE interrupt enable.

TCIE

Bit 6: Transmission complete interrupt enable.

TXEIE

Bit 7: interrupt enable.

PEIE

Bit 8: PE interrupt enable.

PS

Bit 9: Parity selection.

PCE

Bit 10: Parity control enable.

WAKE

Bit 11: Receiver wakeup method.

M0

Bit 12: Word length.

MME

Bit 13: Mute mode enable.

CMIE

Bit 14: Character match interrupt enable.

OVER8

Bit 15: Oversampling mode.

DEDT0

Bit 16: DEDT0.

DEDT1

Bit 17: DEDT1.

DEDT2

Bit 18: DEDT2.

DEDT3

Bit 19: DEDT3.

DEDT4

Bit 20: Driver Enable de-assertion time.

DEAT0

Bit 21: DEAT0.

DEAT1

Bit 22: DEAT1.

DEAT2

Bit 23: DEAT2.

DEAT3

Bit 24: DEAT3.

DEAT4

Bit 25: Driver Enable assertion time.

RTOIE

Bit 26: Receiver timeout interrupt enable.

EOBIE

Bit 27: End of Block interrupt enable.

M1

Bit 28: Word length.

FIFOEN

Bit 29: FIFO mode enable.

TXFEIE

Bit 30: TXFIFO empty interrupt enable.

RXFFIE

Bit 31: RXFIFO Full interrupt enable.

CR2

Control register 2

Offset: 0x4, reset: 0x0000, access: read-write

0/22 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
ADD4_7 rw				ADD0_3 rw				RTOEN rw	ABRMOD1 rw	ABRMOD0 rw	ABREN rw	MSBFIRST rw	TAINV rw	TXINV rw	RXINV rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
SWAP rw	LINEN rw	STOP rw		CLKEN rw	CPOL rw	CPHA rw	LBCL rw		LBDIE rw	LBDL rw	ADDM7 rw	DIS_NSS rw			SLVEN rw

Toggle Fields.

SLVEN

Bit 0: Synchronous Slave mode enable.

DIS_NSS

Bit 3: When the DSI_NSS bit is set, the NSS pin input will be ignored.

ADDM7

Bit 4: 7-bit Address Detection/4-bit Address Detection.

LBDL

Bit 5: LIN break detection length.

LBDIE

Bit 6: LIN break detection interrupt enable.

LBCL

Bit 8: Last bit clock pulse.

CPHA

Bit 9: Clock phase.

CPOL

Bit 10: Clock polarity.

CLKEN

Bit 11: Clock enable.

STOP

Bits 12-13: STOP bits.

LINEN

Bit 14: LIN mode enable.

SWAP

Bit 15: Swap TX/RX pins.

RXINV

Bit 16: RX pin active level inversion.

TXINV

Bit 17: TX pin active level inversion.

TAINV

Bit 18: Binary data inversion.

MSBFIRST

Bit 19: Most significant bit first.

ABREN

Bit 20: Auto baud rate enable.

ABRMOD0

Bit 21: ABRMOD0.

ABRMOD1

Bit 22: Auto baud rate mode.

RTOEN

Bit 23: Receiver timeout enable.

ADD0_3

Bits 24-27: Address of the USART node.

ADD4_7

Bits 28-31: Address of the USART node.

CR3

Control register 3

Offset: 0x8, reset: 0x0000, access: read-write

0/24 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
TXFTCFG rw			RXFTIE rw	RXFTCFG rw			TCBGTIE rw	TXFTIE rw	WUFIE rw	WUS rw		SCARCNT rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DEP rw	DEM rw	DDRE rw	OVRDIS rw	ONEBIT rw	CTSIE rw	CTSE rw	RTSE rw	DMAT rw	DMAR rw	SCEN rw	NACK rw	HDSEL rw	IRLP rw	IREN rw	EIE rw

Toggle Fields.

EIE

Bit 0: Error interrupt enable.

IREN

Bit 1: Ir mode enable.

IRLP

Bit 2: Ir low-power.

HDSEL

Bit 3: Half-duplex selection.

NACK

Bit 4: Smartcard NACK enable.

SCEN

Bit 5: Smartcard mode enable.

DMAR

Bit 6: DMA enable receiver.

DMAT

Bit 7: DMA enable transmitter.

RTSE

Bit 8: RTS enable.

CTSE

Bit 9: CTS enable.

CTSIE

Bit 10: CTS interrupt enable.

ONEBIT

Bit 11: One sample bit method enable.

OVRDIS

Bit 12: Overrun Disable.

DDRE

Bit 13: DMA Disable on Reception Error.

DEM

Bit 14: Driver enable mode.

DEP

Bit 15: Driver enable polarity selection.

SCARCNT

Bits 17-19: Smartcard auto-retry count.

WUS

Bits 20-21: Wakeup from Stop mode interrupt flag selection.

WUFIE

Bit 22: Wakeup from Stop mode interrupt enable.

TXFTIE

Bit 23: threshold interrupt enable.

TCBGTIE

Bit 24: Tr Complete before guard time, interrupt enable.

RXFTCFG

Bits 25-27: Receive FIFO threshold configuration.

RXFTIE

Bit 28: RXFIFO threshold interrupt enable.

TXFTCFG

Bits 29-31: TXFIFO threshold configuration.

BRR

Baud rate register

Offset: 0xC, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRR rw

Toggle Fields.

BRR

Bits 0-15: BRR_4_15.

GTPR

Guard time and prescaler register

Offset: 0x10, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
GT rw								PSC rw

Toggle Fields.

PSC

Bits 0-7: Prescaler value.

GT

Bits 8-15: Guard time value.

RTOR

Receiver timeout register

Offset: 0x14, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
BLEN rw								RTO rw
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RTO rw

Toggle Fields.

RTO

Bits 0-23: Receiver timeout value.

BLEN

Bits 24-31: Block Length.

RQR

Request register

Offset: 0x18, reset: 0x0000, access: write-only

0/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
											TXFRQ w	RXFRQ w	MMRQ w	SBKRQ w	ABRRQ w

Toggle Fields.

ABRRQ

Bit 0: Auto baud rate request.

SBKRQ

Bit 1: Send break request.

MMRQ

Bit 2: Mute mode request.

RXFRQ

Bit 3: Receive data flush request.

TXFRQ

Bit 4: Transmit data flush request.

ISR

Interrupt & status register

Offset: 0x1C, reset: 0x00C0, access: read-only

28/28 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
				TXFT r	RXFT r	TCBGT r	RXFF r	TXFE r	REACK r	TEACK r	WUF r	RWU r	SBKF r	CMF r	BUSY r
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ABRF r	ABRE r	UDR r	EOBF r	RTOF r	CTS r	CTSIF r	LBDF r	TXE r	TC r	RXNE r	IDLE r	ORE r	NF r	FE r	PE r

Toggle Fields.

PE

Bit 0: PE.

FE

Bit 1: FE.

NF

Bit 2: NF.

ORE

Bit 3: ORE.

IDLE

Bit 4: IDLE.

RXNE

Bit 5: RXNE.

TC

Bit 6: TC.

TXE

Bit 7: TXE.

LBDF

Bit 8: LBDF.

CTSIF

Bit 9: CTSIF.

CTS

Bit 10: CTS.

RTOF

Bit 11: RTOF.

EOBF

Bit 12: EOBF.

UDR

Bit 13: SPI slave underrun error flag.

ABRE

Bit 14: ABRE.

ABRF

Bit 15: ABRF.

BUSY

Bit 16: BUSY.

CMF

Bit 17: CMF.

SBKF

Bit 18: SBKF.

RWU

Bit 19: RWU.

WUF

Bit 20: WUF.

TEACK

Bit 21: TEACK.

REACK

Bit 22: REACK.

TXFE

Bit 23: TXFIFO Empty.

RXFF

Bit 24: RXFIFO Full.

TCBGT

Bit 25: Transmission complete before guard time flag.

RXFT

Bit 26: RXFIFO threshold flag.

TXFT

Bit 27: TXFIFO threshold flag.

ICR

Interrupt flag clear register

Offset: 0x20, reset: 0x0000, access: write-only

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
											WUCF w			CMCF w
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		UDRCF w	EOBCF w	RTOCF w		CTSCF w	LBDCF w	TCBGTCF w	TCCF w	TXFECF w	IDLECF w	ORECF w	NCF w	FECF w	PECF w

Toggle Fields.

PECF

Bit 0: Parity error clear flag.

FECF

Bit 1: Framing error clear flag.

NCF

Bit 2: Noise detected clear flag.

ORECF

Bit 3: Overrun error clear flag.

IDLECF

Bit 4: Idle line detected clear flag.

TXFECF

Bit 5: TXFIFO empty clear flag.

TCCF

Bit 6: Transmission complete clear flag.

TCBGTCF

Bit 7: Transmission complete before Guard time clear flag.

LBDCF

Bit 8: LIN break detection clear flag.

CTSCF

Bit 9: CTS clear flag.

RTOCF

Bit 11: Receiver timeout clear flag.

EOBCF

Bit 12: End of block clear flag.

UDRCF

Bit 13: SPI slave underrun clear flag.

CMCF

Bit 17: Character match clear flag.

WUCF

Bit 20: Wakeup from Stop mode clear flag.

RDR

Receive data register

Offset: 0x24, reset: 0x0000, access: read-only

1/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							RDR r

Toggle Fields.

RDR

Bits 0-8: Receive data value.

TDR

Transmit data register

Offset: 0x28, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
							TDR rw

Toggle Fields.

TDR

Bits 0-8: Transmit data value.

PRESC

Prescaler register

Offset: 0x2C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												PRESCALER rw

Toggle Fields.

PRESCALER

Bits 0-3: Clock prescaler.

USB

0x40006800: Universal serial bus full-speed device interface

21/167 fields covered. Toggle Registers.

EP0R

endpoint 0 register

Offset: 0x0, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle Fields.

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP1R

endpoint 1 register

Offset: 0x4, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle Fields.

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP2R

endpoint 2 register

Offset: 0x8, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle Fields.

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP3R

endpoint 3 register

Offset: 0xC, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle Fields.

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP4R

endpoint 4 register

Offset: 0x10, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle Fields.

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP5R

endpoint 5 register

Offset: 0x14, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle Fields.

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP6R

endpoint 6 register

Offset: 0x18, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle Fields.

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

EP7R

endpoint 7 register

Offset: 0x1C, reset: 0x00000000, access: read-write

0/10 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR_RX rw	DTOG_RX rw	STAT_RX rw		SETUP rw	EP_TYPE rw		EP_KIND rw	CTR_TX rw	DTOG_TX rw	STAT_TX rw		EA rw

Toggle Fields.

EA

Bits 0-3: Endpoint address.

STAT_TX

Bits 4-5: Status bits, for transmission transfers.

DTOG_TX

Bit 6: Data Toggle, for transmission transfers.

CTR_TX

Bit 7: Correct Transfer for transmission.

EP_KIND

Bit 8: Endpoint kind.

EP_TYPE

Bits 9-10: Endpoint type.

SETUP

Bit 11: Setup transaction completed.

STAT_RX

Bits 12-13: Status bits, for reception transfers.

DTOG_RX

Bit 14: Data Toggle, for reception transfers.

CTR_RX

Bit 15: Correct transfer for reception.

CNTR

control register

Offset: 0x40, reset: 0x00000003, access: read-write

0/15 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTRM rw	PMAOVRM rw	ERRM rw	WKUPM rw	SUSPM rw	RESETM rw	SOFM rw	ESOFM rw	L1REQM rw		L1RESUME rw	RESUME rw	FSUSP rw	LPMODE rw	PDWN rw	FRES rw

Toggle Fields.

FRES

Bit 0: Force USB Reset.

PDWN

Bit 1: Power down.

LPMODE

Bit 2: Low-power mode.

FSUSP

Bit 3: Force suspend.

RESUME

Bit 4: Resume request.

L1RESUME

Bit 5: LPM L1 Resume request.

L1REQM

Bit 7: LPM L1 state request interrupt mask.

ESOFM

Bit 8: Expected start of frame interrupt mask.

SOFM

Bit 9: Start of frame interrupt mask.

RESETM

Bit 10: USB reset interrupt mask.

SUSPM

Bit 11: Suspend mode interrupt mask.

WKUPM

Bit 12: Wakeup interrupt mask.

ERRM

Bit 13: Error interrupt mask.

PMAOVRM

Bit 14: Packet memory area over / underrun interrupt mask.

CTRM

Bit 15: Correct transfer interrupt mask.

ISTR

interrupt status register

Offset: 0x44, reset: 0x00000000, access: Unspecified

3/11 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
CTR r	PMAOVR rw	ERR rw	WKUP rw	SUSP rw	RESET rw	SOF rw	ESOF rw	L1REQ rw			DIR r	EP_ID r

Toggle Fields.

EP_ID

Bits 0-3: Endpoint Identifier.

DIR

Bit 4: Direction of transaction.

L1REQ

Bit 7: LPM L1 state request.

ESOF

Bit 8: Expected start frame.

SOF

Bit 9: start of frame.

RESET

Bit 10: reset request.

SUSP

Bit 11: Suspend mode request.

WKUP

Bit 12: Wakeup.

ERR

Bit 13: Error.

PMAOVR

Bit 14: Packet memory area over / underrun.

CTR

Bit 15: Correct transfer.

FNR

frame number register

Offset: 0x48, reset: 0x0000, access: read-only

5/5 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RXDP r	RXDM r	LCK r	LSOF r		FN r

Toggle Fields.

FN

Bits 0-10: Frame number.

LSOF

Bits 11-12: Lost SOF.

LCK

Bit 13: Locked.

RXDM

Bit 14: Receive data - line status.

RXDP

Bit 15: Receive data + line status.

DADDR

device address

Offset: 0x4C, reset: 0x0000, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								EF rw	ADD rw

Toggle Fields.

ADD

Bits 0-6: Device address.

EF

Bit 7: Enable function.

BTABLE

Buffer table address

Offset: 0x50, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BTABLE rw

Toggle Fields.

BTABLE

Bits 3-15: Buffer table.

COUNT0_TX

Transmission byte count 0

Offset: 0x52, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT0_TX rw

Toggle Fields.

COUNT0_TX

Bits 0-9: Transmission byte count.

LPMCSR

control and status register

Offset: 0x54, reset: 0x0000, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								BESL r				REMWAKE rw		LPMACK rw	LPMEN rw

Toggle Fields.

LPMEN

Bit 0: LPM support enable.

LPMACK

Bit 1: LPM Token acknowledge enable.

REMWAKE

Bit 3: RemoteWake value.

BESL

Bits 4-7: BESL value.

COUNT0_RX

Reception byte count 0

Offset: 0x56, reset: 0x0000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT0_RX r

Toggle Fields.

COUNT0_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

BCDR

Battery charging detector(

Offset: 0x58, reset: 0x0000, access: Unspecified

4/9 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DPPU rw								PS2DET r	SDET r	PDET r	DCDET r	SDEN rw	PDEN rw	DCDEN rw	BCDEN rw

Toggle Fields.

BCDEN

Bit 0: Battery charging detector (BCD) enable.

DCDEN

Bit 1: Data contact detection (DCD) mode enable.

PDEN

Bit 2: Primary detection (PD) mode enable.

SDEN

Bit 3: Secondary detection (SD) mode enable.

DCDET

Bit 4: Data contact detection (DCD) status.

PDET

Bit 5: Primary detection (PD) status.

SDET

Bit 6: Secondary detection (SD) status.

PS2DET

Bit 7: DM pull-up detection status.

DPPU

Bit 15: DP pull-up control.

COUNT1_TX

Transmission byte count 0

Offset: 0x5A, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT1_TX rw

Toggle Fields.

COUNT1_TX

Bits 0-9: Transmission byte count.

ADDR1_RX

Reception buffer address 0

Offset: 0x5C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR1_RX rw

Toggle Fields.

ADDR1_RX

Bits 1-15: Reception buffer address.

COUNT1_RX

Reception byte count 0

Offset: 0x5E, reset: 0x0000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT1_RX r

Toggle Fields.

COUNT1_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT2_TX

Transmission byte count 0

Offset: 0x62, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT2_TX rw

Toggle Fields.

COUNT2_TX

Bits 0-9: Transmission byte count.

ADDR2_RX

Reception buffer address 0

Offset: 0x64, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR2_RX rw

Toggle Fields.

ADDR2_RX

Bits 1-15: Reception buffer address.

COUNT2_RX

Reception byte count 0

Offset: 0x66, reset: 0x0000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT2_RX r

Toggle Fields.

COUNT2_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT3_TX

Transmission byte count 0

Offset: 0x6A, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT3_TX rw

Toggle Fields.

COUNT3_TX

Bits 0-9: Transmission byte count.

ADDR3_RX

Reception buffer address 0

Offset: 0x6C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR3_RX rw

Toggle Fields.

ADDR3_RX

Bits 1-15: Reception buffer address.

COUNT3_RX

Reception byte count 0

Offset: 0x6E, reset: 0x0000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT3_RX r

Toggle Fields.

COUNT3_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT4_TX

Transmission byte count 0

Offset: 0x72, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT4_TX rw

Toggle Fields.

COUNT4_TX

Bits 0-9: Transmission byte count.

ADDR4_RX

Reception buffer address 0

Offset: 0x74, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR4_RX rw

Toggle Fields.

ADDR4_RX

Bits 1-15: Reception buffer address.

COUNT4_RX

Reception byte count 0

Offset: 0x76, reset: 0x0000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT4_RX r

Toggle Fields.

COUNT4_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT5_TX

Transmission byte count 0

Offset: 0x7A, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT5_TX rw

Toggle Fields.

COUNT5_TX

Bits 0-9: Transmission byte count.

ADDR5_RX

Reception buffer address 0

Offset: 0x7C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR5_RX rw

Toggle Fields.

ADDR5_RX

Bits 1-15: Reception buffer address.

COUNT5_RX

Reception byte count 0

Offset: 0x7E, reset: 0x0000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT5_RX r

Toggle Fields.

COUNT5_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT6_TX

Transmission byte count 0

Offset: 0x82, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT6_TX rw

Toggle Fields.

COUNT6_TX

Bits 0-9: Transmission byte count.

ADDR6_RX

Reception buffer address 0

Offset: 0x84, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR6_RX rw

Toggle Fields.

ADDR6_RX

Bits 1-15: Reception buffer address.

COUNT6_RX

Reception byte count 0

Offset: 0x86, reset: 0x0000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT6_RX r

Toggle Fields.

COUNT6_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

COUNT7_TX

Transmission byte count 0

Offset: 0x8A, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
						COUNT7_TX rw

Toggle Fields.

COUNT7_TX

Bits 0-9: Transmission byte count.

ADDR7_RX

Reception buffer address 0

Offset: 0x8C, reset: 0x0000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADDR7_RX rw

Toggle Fields.

ADDR7_RX

Bits 1-15: Reception buffer address.

COUNT7_RX

Reception byte count 0

Offset: 0x8E, reset: 0x0000, access: Unspecified

1/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BL_SIZE rw	NUM_BLOCK rw					COUNT7_RX r

Toggle Fields.

COUNT7_RX

Bits 0-9: Reception byte count.

NUM_BLOCK

Bits 10-14: Number of blocks.

BL_SIZE

Bit 15: Block size.

VREFBUF

0x40010030: Voltage reference buffer

1/5 fields covered. Toggle Registers.

CSR

VREF control and status register

Offset: 0x0, reset: 0x00000002, access: Unspecified

1/4 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												VRR r	VRS rw	HIZ rw	ENVR rw

Toggle Fields.

ENVR

Bit 0: Voltage reference buffer enable.

HIZ

Bit 1: High impedance mode.

VRS

Bit 2: Voltage reference scale.

VRR

Bit 3: Voltage reference buffer ready.

CCR

calibration control register

Offset: 0x4, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
										TRIM rw

Toggle Fields.

TRIM

Bits 0-5: Trimming code.

WWDG

0x40002C00: System window watchdog

0/6 fields covered. Toggle Registers.

CR

Control register

Offset: 0x0, reset: 0x0000007F, access: read-write

0/2 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
								WDGA rw	T rw

Toggle Fields.

T

Bits 0-6: 7-bit counter (MSB to LSB).

WDGA

Bit 7: Activation bit.

CFR

Configuration register

Offset: 0x4, reset: 0x0000007F, access: read-write

0/3 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
		WDGTB rw				EWI rw			W rw

Toggle Fields.

W

Bits 0-6: 7-bit window value.

EWI

Bit 9: Early wakeup interrupt.

WDGTB

Bits 11-13: Timer base.

SR

Status register

Offset: 0x8, reset: 0x00000000, access: read-write

0/1 fields covered.

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
															EWIF rw

Toggle Fields.

EWIF

Bit 0: Early wakeup interrupt flag.